Function block library
7-218
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SHB9300CRV EN 2.0
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The current phase signal is output to STORE1-ACT.
1. A LOW-HIGH edge at the TP input E5 saves the last phase signal and supplies it to
STORE1-PH1.
2. STORE1-ENTP = LOW-HIGH edge enables the TP input E5 for the next triggering.
3. Another LOW-HIGH edge at the TP input E5 saves the last phase signal.
– STORE1-PH1 outputs this last phase signal.
– STORE1-PH2 outptus the last but one phase signal.
– STORE1-PHDIFF outputs the difference between STORE1-PH1 and STORE1-PH2.
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STORE1-RESET = HIGH resets memory, counter, integrators and enables the TP input E5 for
the triggering.
Output of the difference of the two saved phase signals
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A two-step counter controls the output at STORE1-PHDIFF.
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Every second triggering via the PT input E5 results in another output to STORE1-PHDIFF.
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STORE1-LOAD0 = HIGH resets the counter.
Additional control
1. STORE1-LOAD1 = LOW-HIGH edge, sets the counter to the first step (preparation of the
output to STORE1-PHDIFF)
2. A triggering via TP input E5 sets the counter to the second step (output to STORE1-PHDIFF).
Tip!
If STORE1-LOAD1 is set cyclically, STORE1-PHDIFF supplies a new difference signal after every
triggering.
7.6.72.3 Save STORE2 phase signal
A phase signal at MCTRL-PHI-ACTis added to aphase signal. The following sequence indicates the
ways of signal output and storage.
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The current phase signal is output to STORE2-ACT.
1. A LOW-HIGH edge at the TP input E4 saves the last phase signal and supplies it to
STORE2-PH1.
2. STORE2-ENTP = LOW-HIGH edge enables the TP input E4 for the next triggering.
3. Another LOW-HIGH edge at the TP input E4 saves the last phase signal.
– STORE2-PH1 outputs this last phase signal.
– STORE2-PH2 outputs the last but one phase signal.
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STORE2-RESET = HIGH resets memory and integrator and enables the TP input E4 for the
triggering.