2 3 4
LMS
Action
It
does, however,
generate
the Memory Parity
Error signal. The basic processor inhibits
the
trap
that
would ordinarily
occur
for the mem-
ory parity error.
o 0 0
Clear
memory - stores zero
in
the
memory
location specified by the address.
o 0 Reserved.
o 0 0 Reserved.
o 0 Reserved.
o 0
Read
write lock - loads a pair
of
4-bit
write
locks into byte 3 of R (bits 24-31) and 0
in
all
other
bit positions
of
R.
The write lock stored
in bits
24-27
is
stored in
the
memory system1s
Write Lock memory
at
the location correspond-
ing to bits 17-21 of
the
effective
address,
bit
22=0.
The write lock stored in bits 28-31
corresponds to bits 17-21 of the
effective
ad-
dress,
bit
22=1.
o Write write lock - stores byte 3
of
the
data
word sent to memory as a pair of write locks
in the memory system's Write
Lock
memory
at
a location corresponding to bits 17-21
of
the
effective
address, bit
22=0
(for
data
bits 24-27)
and
bits 17-21 of
the
effective
address,
bit
22=1
(for
data
bits
28-31).
1 0 0 0 Read status word
ot
- loads status word 0 into
R (see Table 9).
o 0 Reserved.
o 0 Read status word 1t - loads status word 1 into
R (see Table 10).
o Reserved.
o 0
Read
status word 0 and
clear.
o Reserved.
o Write double error - stores an arbitrary word
into a specified memory
location,
with two
differences compared to a normal Write Word
instruction: (1) Byte 3
in
memory
is
forced to
zero; (2)
the
arbitrary
word
is
stored
in
memory
with an intentional wrong parity; on a
sub-
sequent read of
that
word, the memory issues
the
parity error signal.
Reserved.
Condition code settings
after
execution.
t Primarily of diagnostic concern.
102 Control Instructions
Table
9.
Status Word 0
Field
Bits
Comments
0
Reserved
1 Power status
2-7
Memory
un
i t error cod e
8-9
Memory type
Ports
10
Port 1
enabled
11
Port 2
enabled
12
Port 3 ena
bl
ed
13
Port 4 enabled
14
Port 5 ena
bl
ed
15
Port 6
enabled
16
Port 1 servi ced
17
Port 2 serviced
18
Port 3 serviced
19
Port 4 serviced
20
Port 5 serv iced
21
Port 6 serv iced
Memory fau I t
22
0
types
23
Uncorrectable memory unit error
24
Memory module
selection
error
25
Address parity error
26
Data in parity error
27
Write lock
parity
error
28 Port
selection
error
29
Undefined operation
30
Control error
31
Multiple error
For
"read and inhibit
parity"
operations, the status of the
word loaded
(if
any)
is
stored
in
the condition code bits
at
the
conclusion of
execution
as follows:
CC
i:
Memory Parity Error (from memory)
CC2: Data
Bus
Check (from CPU)
CC3:
Parity
Bit
(from memory)
CC4: 0
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