The control and
immediate
results
of
this
instruction
reside
in
registers
and
memory; thus, the
instruction
can
be
interrupted
between
the
completion
of
one
iteration
(oper-
and
execution
cycle)
and
that
time (during
the
next
itera-
tion)
when
a memory
location
or register
is
modified.
If
an
interrupt
occurs during this time, the
current
iteration
is
aborted
and
the instruction address
portion
of
the
program
status words
(PSWs) remains
pointing
to
the
interrupted
in-
struction.
After
the
interrupt-servicing
routine
is
comple-
ted,
the
instruction continues,
from
the
point
at
which
it
was
interrupted
and does not
begin
anew.
SINGLE-INSTRUCTION
INTERRUPTS
A
single-instruction
interrupt
occurs in this
situation:
an
interrupt
level
is
activated,
the
current
program
is
inter-
rupted,
the
single
instruction
in
the
interrupt
location
is
executed,
the
interrupt
level
is
automatically
cleared
and
armed,
and
the
interrupted
program
continues
without
being
disturbed or
delayed
(except
for
the
time required
to
exe-
cute
the
single
instruction).
If
any
of
the
following instructions is
executed
in
any
in-
terrupt
location,
then
the
corresponding
interrupt
is
auto-
matically
a
single-instruction
interrupt:
MODIFY
AND
TEST
BYTE
(MTB)
MODIFY A
ND
TEST
HALFWORD
(M
TH)
MODIFY
AND
TEST
WORD
(MTW)
A modify
and
test
instruction modifies
the
effective
byte,
halfword,
or
word (as
described
in
Chapter
3,
"Fixed-Point
Arithmetic
Instructions") but the
current
condition
code
re-
mains
unchanged
(even
if
overflow
occurs).
The
effective
address
of
a modify and test instruction in
an
interrupt
lo-
cation
(except
counter
4)
is
always
treated
as
an
actual
ad-
dress, regardless of
whether
the
memory map
is
currently
being
used.
Counter
4 uses
the
mapped
location
if mopping
is
currently
invoked (as
specified
in the PSWs). The
exe-
cution
of
a modify
and
test instruction in
an
interrupt
location,
including
mapped
and
unmapped
counter
4,
is
in-
dependent
of
the
virtual memory
access-protection
code
and
the
real
memory
write
lock; thus, a memory
protection
violation
trap
cannot
occur
as
the
resultof
overflow
caused
by
executing
MTH
or
MTW
in
an
interrupt
location.
The
execution
of
a modify
and
test instruction in
an
interrupt
location
automatically
clears
and
arms
the
corresponding
in-
terrupt
level,
allowing
the
interrupted
program to
continue.
When a modify
and
test instruction
is
executed
in a
count-
pulse
interrupt
location,
all
of
the
above
conditions
apply
as
well
as
the
following: If the
resultant
value
in
the
ef-
fective
location
is
zero,
the
corresponding
counter-equals-
zero
interrupt
is
triggered.
36 Trap System
TRAP
SYSTEM
A
trap
is
similar
to
an
interrupt
in
that
when a
trap
condi-
tion
occurs,
program
execution
automatically
branches
to
a
predesignated
location.
A trap differs from
an
interrupt
in
that
a
trap
location
must
contain
an
XPSD or
PSS
instruc-
tion.
The time
of
trap
occurrence
can
vary: The
instruc-
tion in
the
trap
location
can
be
executed
immediately
(i
.e.,
the
current
instruction in
the
program
being
executed
is
aborted),
or
when the
current
instruction has
been
partially
executed,
or upon
completion
of
the
current
instruction.
The
trap
instruction
is
not
held
in
abeyance
by
higher
pri-
ority
traps,
whereas
interrupts possibly may not
be
processed
before
an
entire
sequence
of
instructions
is
executed.
TRAP
ENTRY
SEQUENCE
A
trap
entry
sequence
begins when the
basic
processor
de-
tects
the
trap
condition
and
ends when
the
new program
sta-
tus words (PSWs)
have
successfully
replaced
the old PSWs.
Detection
of
any
condition
(function) listed in Table
3,
which summarizes
the
trap system, results in a trap
to
a
unique
location
in memory. When a trap
condition
occurs,
the
basic
processor sets the
trap
state.
The
operation
the
basic
processor
is
currently
performing
mayor
may not
be
carried
to
completion,
depending
on
the
type
of
trap
and
the
opera
tion bei
ng
performed.
In
any
event,
the
program
instruction
is
terminated
with a trap
sequence
(branch to the
appropriate
trap
location).
During this
sequence
the
pro-
gram
counter
is
not
advanced;
instead,
the X
PSD
instruction
in
the
trap
location
is
executed.
If
any
interrupt
level
is
ready
to
move
to
the
active
state
at
the
same time
an
XPSD
trap
instruction
is
in process,
the
interrupt
acknowledgment
will not
occur
until
the
XPSD
trap instruction
is
completed.
Should a trap
location
not
contain
an
XPSD or
PSS
instruc-
tion,
a second trap
sequence
is
immediately invoked (see
"Instruction Exception Trap"
later
in this
chapter).
TRAP
ADDRESSING
Trap addressing is
described
under
"Interrupt
and
Trap Entry
Addressing
II
•
TRAP
MASKS
The programmer may mask
the
four
trap
conditions
described
below
in
the
program status words
(PSWs)
or
the
stack
pointer
doubleword,
as
appropriate;
other
traps
cannot
be
masked.
1.
The push-down
stack
limit
trap
is masked within the
stack
pointer
doubleword for
each
individual
stack.
2. The
fixed-point
overflow trap is masked in
bit
posi-
tion
11
(AM)
of
the
PSWs.
If this
bit
position
contains
a
zero,
the
trap
is
allowed
to
occur;
if
bit
11
contains
To Next Page
Loading...
Need help?
General