PORTS
AND
MEMORY
BUSES
A memory
unit
may
contain
two, four, or six ports, which
have
a fixed
priority
order for
the
resolution
of
access
con-
tention.
Each port
allows
the
memory
unit
to
communicate
via
a memory bus
with
a
different
external
system
(i.e.,
a
processor
cluster),
which
communicates
with
the
mem-
ory bus
via
the
Memory
Interface
(MI) (see Figure
4).
Ports
are
numbered from 1 (top priority)
to
6 (lowest
priority).
The
selection
logic
is
biased
to
select
port
1 (the fast port)
whenever
the
memory is
quiescent.
Thus
performance
is
improved for
the
Memory
Interface
(MI)
connected
to
that
port,
and
hence
to
the
processors
connected
to
that
MI.
A memory reserve
function
insures proper
execution
of
in-
structions
that
require
guaranteed
re-access
to a memory
locati
on
before
a
second
processor
can
access
it.
Each
port
is
equipped
with
an
inhibit
function
that
can
be
activated
from
the
Configuration
Control Panel (see
Chapter
6).
Other
major functions performed by
the
ports
are:
1.
Address
recognition.
2.
Address
interleaving.
The memory system
is
bui It up by
interconnection
of
identi-
cally
numbered ports of
all
memory
units.
Each
intercon-
necting
cable
is
called
a memory bus,
wh
ich
is
dedicated
to a
single
processor
cluster
(see Figure
4).
PORT
PRIORITY
The
multiport
structure
allows
two simul
taneous
requests for
memory
to
be
processed
immediately
if
the
requests
are
received
on
different
ports for
different
memory
units,
and
neither
memory
unit
is
busy.
If a
requested
memory
unit
is
busy
or
receives
simultaneous requests,
the
memory port
logic
selects
the
highest
priority
request
first.
Normally,
all
ports in a memory
unit
operate
on
the
fixed
priority
basis (the fast port has
the
highest
priority
and
the
highest-numbered
normal port
the
lowest).
Thus,
if
a
single
memory
unit
simultaneously
receives
requests on port 2
and
port
4,
port
2 has first
access
to
the
memory
unit.
Each
port
also
has
associated
with it a
high-priority
line
which,
upon
receiving
a
high-priority
request,
raises
the
port's
priority
above
that
of
all
other
ports
except
for
any
higher
priority
port,
which
also
has a
high-priority
request
on its
line.
MEMORY INTERLEAVING
Memory
interleaving
is
a
hardware
feature
that
distributes
sequential
addresses
into
two
independently
operating
mem-
ory units.
Interleaving
increases
the
probability
that
a processor
(i.e.,
basic processor
or
MIOP)
can
gain
16
Main Memory
access
to a
given
memory
location
without
encountering
interference
from
another
processor
that
is
making
sequen-
tia
I
requests.
Two
memory units
of
the
same
size
can
be
two-way
inter-
leaved.
Both memory units transform
an
incoming address,
as
follows:
Size
of
Each
Memory
Unit
32K
16K
Address Bits
Interchanged
16
and
31
17
and
31
As
a result
of
the
address transformation,
even
incoming
ad-
dresses
are
assigned
to
one
memory
unit
and
odd incoming
addresses to
the
other.
Note
that
the
incoming address
(un-
transformed)
is
stored in
the
status
register
of
the
accessed
unit
in
each
cycle
and
is
avai
lable
as
are
other
types
of
dy-
namic
status
information.
(Interleaved
memory units
have
two
status
registers,
one
in
each
of
the
un
its.)
MEMORY UNIT STARTING
ADDRESS
Each memory
unit
is
individually
identified
by
starting
ad-
dress
switches
located
on
the
Configuration
Control Panel
(see
Chapter
6).
These switches
define
the
range
of
ad-
dresses
the
memory
unit
responds to
when
servicing
memory
requests.
All addresses,
including
the
starting
address, for
a
given
memory
unit
are
the
same for
all
ports in
that
unit;
that
is,
the
address
of
a
given
word remains
the
same
re-
gard
less
of
the
port
used to
access
the
word.
The
starti
ng
address
of
a memory
unit
must
be
on a
boundary
equal
to a
multiple
of
the
size
of
the
memory
unit
when
two memory
units (of
the
same
size)
are
interleaved.
The
starting
ad-
dress
of
one
memory
unit
must
be
a
multiple
of
the
size
of
the two memory units
together;
the
second
memory
unit
must
have
a
starting
address
higher
than
that
of
its companion by
its own
size.
Another
way to say this
is
that
the
starting
address for
the
combined units must
be
on
a boundary
equal
to a
multiple
of
the
total
size
of
the
interleaved
assembly.
MAINTAINABILITY
AND
PERFORMANCE
Memory
maintainability
is
enhanced
by
the
following
features:
1.
Error
detection.
Each memory
unit
senses
and
remem-
bers
parity
errors in
the
CMM
data
as well
as
parity
errors in
the
address word
or
the
memory bus
data,
port
selection
errors, CMM
selection
error,
and
undefined
operations.
This status information
is
available
to
di-
agnostic
programs
to
facilitate
error
localization
in
space and time
of
occurrence. The memor; unit
senses
and
reports,
but
does
not
remember (for
diagnostic
pur-
poses) a
write
lock
violation.
2.
Modularity.
For
ease
of
replacement,
the logic
and
stor-
age
circuitry
is
packaged
on modules
that
are
removable
from
backpanelswithoutrequiring
cable
disconnections.
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