level within the interrupt system (location XISC') is armed,
enabled, and not inhibited, the request
wi
II
be processed
by
the
BP
in accordance with the priority that prevails
within the interrupt system, the
lOPs, and the
I/o
sub-
channels within an
MIOP.
The
occurrence
of
.an
I/O
interrupt because of a Stop command is reported as status
information (bit position 7 of register
R)
when the
BP
executes an AIO instruction (normally part
of
an
I/O
handling routine).
Bi
t positi ons
1-7
must
be coded as zeros.
Bi
t posi
ti
ons 8-31
and 40-63 are ignored; but
it
is recommended
that
they also
be coded as zeros.
Bit
positions 32-39 are ,device
depen-
dent
and must be coded as specified in the appropriate
pe-
ripheral reference manual.
The
Stop command is primari
Iy
used to terminate a command
chain for an unbuffered
device,
as i
"ustrated
in the first
example given for the Transfer in Channel command.
Note
that
not
a"
devices recognize the Stop order.
I/O
OPERATION
PHASES
This
section describes the general sequence of events (or
phases) of any
I/o
operation performed
by
an
lOP,
the
function performed
by
the
BP,
lOP,
and
device
controller/
device
during each phase, and a description of
each
type
of
I/O
operation including the applicabi lity of parameters
that
may
be contained within a typical operational
10CD.
For explanation purposes,
each
I/o
operation has five
ma-
jor phases: preparation, initiation, fetching, executing,
and termination phase.
Each phase is furtner described
below.
PREPARATION
PHASE
Before
an
I/o
operation may be performed
by
an
lOP,
an
appropriate command list
must
reside in main memory.
INITIATION
PHASE
Assuming
that
an appropriate command list resides in main
memory,
an
I/O
operation
is
initiated
only if the
BP
ex-
ecutes
an
510
instruction that
is
accepted
by
the addressed
lOP,
device
controller, and device.
The
acceptance
or
rejection
of
an SIO instruction is contingent upon
condi-
tions within the addressed lOP,
device
controller, and
device and is indicated by the condition codes
at
the com-
pletion
of
the SIO instruction.
In
either
case,
the
BP
is
able
to perform
other
instructions or tasks immediately
after
executing an
SIO
instruction. (Refer to
"510"
instruction,
Chapter
3,
for further detai
Is.
)
A successful
SIO instruction causes the addressed
device
to
go
from
the "ready" condition to the
II
busy
II
condition.
FETCHING
PHASE
AI
though
the
services of the
BP
are
not requ ired duri
ng
this phase, the
BP
may
at
any time
execute
either
a TIO,
TDY,
or
POL
instruction without interfering with
the
I/O
operation. However, excessive TIOs and
TDVs
may
cause
a
data
overrun condition. The
BP
may
also
execute
either
an HIO or
RIO
instruction and stop the
I/O
operation.
(An
HIO may leave the
device
in an unpredictable state; an
RIO
resets all controllers and devices on the addressed lOP. )
As
a result
of
accepting an SIO instruction, a command
ad-
dress register within the
I/O
subchannel (assigned to
con-
trol the addressed
device
controller/device)
is
loaded with
the first command doubleword address, the content
of
Gen-
eral Register 0 when the
SIO
instruction
is
accepted.
At
the appropriate time, as determined
by
the priority, the
device
controller/device
wi
II
request
that
the lOP access
main memory and fetch the first word
of
the 10CD
from
an
even memory word location and increment the command
address register by one.
The
disposition
of
the first word
is
dependent upon the contents
of
the first word.
If
the order field contains an
I/O
order for a
device
controller/device,
the
content
of
the order field is
either
loaded into an order register within the appropriate
device
controller/devi ce or ignored (if the 10CD
is
being fetched
for a
data
chained operation).
If
the order is a
Read
Back-
ward order, a control flag is also set within the
lOP
which
allows the memory byte address to be decremented rather
than incremented during the
data
transfer.
For
all orders (excluding the Transfer in Channel command,
described below), the contents
of
bit
positions 10-31 of the
first word
is
loaded into a memory byte address register
of
an
apprapriure
i/O
:)ubd,unnt::L Dt::peflJifl9 vjJVfl
tho::
Vo
order, as described under "Execution Phase", the
content
of
the memory byte address register may be used or ignored. If
used,
it
specifies which memory word location
is
to be
ac-
cessed and also the number
of
bytes of
data
(or control
in-
formation) to be transferred into or
out
of
that
location.
If
the order field contains a Transfer
in
Channel command,
it
is recognized and executed immediately by the lOP.
The
content
of
bit
positions 13-31 (designated as the "next
com-
mand doubleword address" field)
is
loaded directly into the
command address register.
The
Transfer in Channel
com-
mand
is
recognized and
executed
by the
lOP,
it
is
fetched
and executed as the result of fetching one word (rather
than
two), and
it
is transparent
to
the
device
controller/device
(that is,
it
is
executed without affecting
the
continuity of
an
order
that
is
data
chained or
an
I/O
operation that is
command chained). Note: Although
bit
positions 0-3
and
8-12
are
currently ignored,
it
is recommended
that
they
be coded as zeros.
Immediately after executing a Transfer in Channel command,
the
lOP will automatically fetch the first word
of
the next
10CD
as specified
by
the contents
of
the "next command
doub
I eword address" fie I
d.
If the orderfi e I d
of
the
nextI
OC
D
also contains a Transfer in
Channel command, the
I/O
opera-
tion
is
terminated immediately and the lOP enters a Halt
state
because an
lOP
control error (IOPCE) occurred (attempting
to
execute
two successive Transfer
in
Channel commands).
I/O
Operation
Phases
131
To Next Page
Loading...
Need help?
General