R1
R2 R3
Meaning
o
The
effective
virtual address
of
the AN
lZ
instruction would have trapped because
it
was
either
nonexistent, memory
protected,
or
had
a
parity
error.
The
CCs
are
indeterminate
since the instruction to be
analyzed
may
not
have been
fetched
(nonexistent memory).
R(l0-3l)
contain
the
effective
virtual address
of
the
AN
lZ
i nstructi on a I i gned as a word
displacement.
If
no
trap condition occurs,
ANlZ
will
execute
normally
and return the
effective
address
of
the instruction
analyzed.
Table 6 shows the instruction
set
as a 4 by 32 matrix {ar-
ranged as a function
of
the operation code}. This
table
also
shows how the instruction
set
is divided into six groups as
a function
of
the addressing type (delineated
by
heavy
lines).
For
example,
if
the operation
code
of
the
analyzed
instruction is
either
X
'
02
1
,
X
'
20', X
'
21
1
,
X
'
22
1
,
or
X
'
23
1
,
then
CCI
is
set
to
1,
CC2 is
set
to
0,
CC3 is
set
to 0 (when
analyzed
instruction specifies
direct
addressing), and CC4
is
set to 1. The decimal
equivalent
of
the condition code
setting for this group
of
immediate, word addressing type
of
instructions
is
shown as a 9 within a
circle.
The
decimal
equivalents
of the
candition
code settings for the
other
five groups
are
shown in the same manner. If the
analyzed
instruction
calls
for
indirect
addressing, CC3 is always
set
to a 1
and
the decimal
value
of
the condition
code
setting
shown in Table 6 should be increased by 2.
Affected:
(R),
CC
Condition
code
settings:
2 3 4 Instruction addressing type
0
0
-
0
Byte
0 0
-
Immediate, byte
0
-
0
Halfword
0
-
0
Word
0
-
1
Immediate, word
-
0
Doubleword
- -
0 -
Direct
addressing
(EWO
= 0)
-
Indirect
addressing
(EWO
=
1)
INT
INTERPRET
(Word
index
alignment)
I . I . _ I _ I I I
I"'"'
OB
I
I{
I X I Reference address I
o 1 2 3
14
5 6 7 8 9
10
11
12 13
14
15116
17 18
19120
21
22
23124
25
26
27128
29
30
31
INTERPRET
loads bits
0-3
of
the
effective
word into the
condition
code,
loads bits 16-31
of
the
effective
word into
bit
positions 16-31
of
register
Ru1
(and loads
OIS
into
bit
positions
0-15
of
register
Ru1,
loads bits
4-15
of
the
58
Fixed-Point
Arithmetic Instructions
effective
word into
bit
positions 20-31
of
register R (and
clears
the remaining bits
of
register
R).
If R is an odd
value,
INT loads bits
0-3
of
the
effective
word into the condition
code,
loads bits 16-31
of
the
effective
word into
bit
posi-
tions 16-31
of
register
R,
and loads
OIS
into
bit
posi-
tions
0-15
of
register R (bits
4-15
of the
effective
word are
ignored in this case).
Affected:
(R),
(Ru1), CC
EW
O
_
3
-CC
EW
4
_
15
_R20_31iO-
R
O
-
19
EW
16-31-
Ru116_31iO
-
Ru1
0
_
15
Condition
code
settings:
2
3
4
Example 1,
even
R field value:
Before
execution
After
execution
EW
XI
12345678
1
XI
12345678
1
(R)
xxxxxxxx
XI
00000234
1
(Ru
1) = xxxxxxxx
X
I 000056 78
1
CC
xxxx 0001
FIXED-POINT
ARITHMETIC
INSTRUCTIONS
The
fixed-point
arithmetic
instructions
are:
Instruction Name Mnemonic
Add Immediate
AI
Add Halfword
AH
Add Word
AW
Add Doubleword
AD
Subtract Halfword
SH
Subtract Word
SW
Subtract Doubleword
SD
iviuitipiy immediate
Mi
Multiply Halfword
MH
Multiply Word
MW
Divide Halfword
DH
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