located
at
effective
address
of
the
instruction.
This
doubleword,
referred
to as a
stack
pointerdoubleword
(SPD),
has
the
following structure:
Bit
positions 15 through
31
of
the
SPD
contain
a
17-bit
address
field
t
that
points to
the
location
of
the word
cur-
rently
at
the
top (highest-numbered address)
of
the
oper-
and
stack.
In
a push
operation,
the
top-of-stack
address
is
incremented
by 1 and then an operand in a
general
reg-
ister is pushed (stored) into
that
location,
thus becoming
the
contents
of
the new top
of
the
stack;
the contents
of
the previous top
of
the
stack
remain
unchanged.
In
a pull
operation,
the
contents
of
the
current
top
of
the
stack
are
pulled
(loaded) into a
general
register
and
then the
top-
of-stack
address
is
decremented
by
1;
the
contents
of
the
stack
remain unchanged.
Bit
positions 33 through
47
of
the SPD, referred to as the
space
count,
contain
a
15-bit
count
(0
to 32,767)
of
the
number
of
word locations
currently
avai
lable
in the region
of
memory
allocated
to the
stack.
Bit
positions
49
through 63
of
the SPD, referred to as the word
count,
contain
a
15-bit
count
(0
to 32,767) of the number
of
words
currently
in
the
stack.
In
a push
operation,
the
space
count
is decremented
by 1
and
the
worcl
count
is
incremented
by
1;
in a pull
oper-
ation,
the
space
count is
incremented
by 1 and the word
count
is
decremented
by
1.
At
the
beginning
of
all
non-
privi leged push-down instructions,
the
space
count
and the
word
count
are
each
f'ested to
determine
whether
the
instruc-
tion would
cause
either
count
field
to be incremented
above
the upper limit
of
2
15
_1
(32,767), or to be decremented
beiow
the
iower iimit
of
O.
if
execution
of
the push-down
instruction would cause
either
count
limit to be
exceeded,
the
basic
processor
unconditionally
aborts
execution
of
the
instruction,
with
the
stack,
the
stack
pointer
doubleword,
and the
contents
of
general
registers
unchanged.
Ordinarily,
the
basic
processor traps to
location
X
'
42
1
after
aborting
a push-down instruction
because
of
impending
stack
limit
overflow
or
underflow,
and
with the condition
code
un-
changed
from
the
value
it
contained
before
execution
of
the instruction.
However, this
trap
action
can
be
selectively
inhibited
by
setting
either
(or both)
of
the
trap
inhibit bits in the
SPD
to
1.
t
For real
extended
mode
of
addressing this
is
a
20-bit
field (12-31); for real and virtual addressing modes
it
is a
17-bit
field (15-31),
80 Push-Down Instructions
(Non-Privi
leged)
Bit
position 32
of
the
SPD, referred to as
the
trap-on-space
(TS)
inhibit
bit,
determines
whether
the
basic
processor will
trap
to location X
'
42
1
as a result
of
impending overflow
or
underflow of the
space
count
(SPD
33
.;.47)' as follows:
TS
Space
count
overflow/underflow
action
o If
the
execution
of
a pull instruction would cause
the
space
count
to
exceed
2
15
-
1
, or
if
the
executi
on
of
a
push instruction would cause
the
space
count
to
be
less than
0,
the
basic
processor traps to
location
X
'
42
1
with
the
condition
code
unchanged.
Instead
of
trapping to
location
X'421, the
basic
pro-
cessor sets
CCl
to 1 and then
executes
the
next
in-
struction in
sequence.
Bit
position
48
of
the
SPD, referred to
as
the
trap-on-word
(TW)
inhibit
bit,
determines
whether
the
basic processor
traps to
location
X
'
42
1
as
a result
of
impending overflow
or
underflow
of
the word
count
(SPD
49-63)'
as fo.llows:
TW
Word
count
overflow/underflow
action
o If
the
execution
of a push instruction would cause
the
word
count
to
exceed
2
15
-
1
,
or
if
the
execution
of
a pull instruction would cause the word
count
to
be
less than
0,
the
basic processor traps
to
location
X
'
42
1
with
the
condition
code
unchanged.
Instead
of
trapping to
location
X'421, the
basic
pro-
cessor sets CC3
to
1
and
then
executes
the
next
instruction in
sequence.
PUSH-DOWN
CONDITION
CODE
SEnlNGS
If
the
execution
of
a push-down instruction is
attempted
and
the
basi c processor traps to
locati
on X'421,
the
condi-
tion
code
remains unchanged from the value
it
contained
immediately before the instruction was
executed.
If
the
execution
of
a push-down instruction is
attempted
and
the
instruction
is
aborted
because
of
impending
stack
iimit
overflow
or
underflow (or both)
but
the push-down
stack
limit trap is
inhibited
by one (or both)
of
the
inhibits
(TS
and
TW),
then,
CCl
or
CC3 is
set
to 1 (or both
are
set
to
lis)
to
indicate
the
reason for
aborting
the
push-down
instruction, as follows:
o
2 3 4 Reason for
abort
Impending overflow
of
word
count
on a push
operation
or
impending underflow
of
word
count
on a pull
operation.
The push-down
stack
limit trap was
inhibited
by
the
TW
bit
(SPD
48)'
o - Impending overflow
of
space
count
on a pull
operation
or
impending underflow
of
space
count
on a push
operation.
The push-down
stack
limit trap was
inhibited
by
the
TS
bit
(
SPD
32)·
To Next Page
Loading...
Need help?
General