Xerox 550 User Manual

3. Diagnostic logic. Each memory driver module carries
logic used exclusively for localizing faulty elements
in that module. The benefit derived from this diagnos-
tic logic depends on such external factors as the ac-
cessibility to a module tester.
Memory system performance depends on these factors;
1. Access time of memory unit.
2. Cycle time of memory unit.
3. Type of cycle requested.
4. Number of memory units.
5. Interleaving.
6. Type of port (fast or norma I) selected.
7. Self or mutual interference between memory requests.
All these factors characterize not only memory performance
but a Iso system performance.
Port access time and cycle time are essential memory speed
characteristics pertaining to CMM operations.
1. Port access time. This is the time interval measured
between the clock pulse that transmits an address word
from
the Memory Interface (MI) to an idle memory unit
and the clock pulse that translates a memory word from
the same memory unit to the MI.
2.
- I.. ,... I._ I 1.1 ,_ I
'-ycte TIme. '-ycte TIme aepenas on rne ope'Uliun [}~-
ing performed and on the sequence of operation. Cycle
time determines the maximum rate at which a memory
un
it can accept requests.
VIRTUAL AND REAL MEMORY
Virtual memory is the address space available to an in-
dividual program. The maximum size of virtual memory is
128K words, broken into as many as 256 pages of 512 words
each distributed throughout the available pages of real
memory.
Real memory corresponds
to the physical memory, and its size
is equal to the total number of words contained within all
memory units in the system. The size of real memory ranges
from a minimum
of 16K words to a maximum of 256K words.
Note: Real memory address space is 1 million words.
MEMORY REFERENCE ADDRESS
Memory
locations 0 through 15 are not normally accessible
to the programmer because their memory addresses are re-
served as register designators for "register-te-register
ll
op-
erations. Nevertheless an instruction treats any of the
first 16 registers of the current register block as if it were
a location in main memory. Furthermore, the register block
can hold an instruction (or a series of as many as 16 instruc-
tions) for execution just as though the instruction (or instruc-
ti ons) were in ma in memory.
The
following terms are used in the various types of address-
ing described in subsequent sections. See also Figure 5,
wh ich illustrates the control and data flow during address
generation.
1 • Instructi on Address. Th is is the address of the next
instruction to be executed. For real, real-extended,
and virtual addressing the 17-bit instruction address is
contained within bits 15-31 of the program status words
(PSWs)
•
2. Reference Address. This is the 17-bit or 20-bit address
associated with any instruction (except that in a trap
or interrupt location that has a 0 in bit position 10).
For real, real extended, direct, and virtual addressing,
the reference address is the address contained within
bits 15-31 of the instruction itself.
The reference address may be modified by using indirect
addressing, indexing, and memory mapping. A refer-
ence address becomes an effective virtual address after
the indirect addressing and/or postindexing (if re-
quired) is performed.
3. 20-Bit Trap or Interrupt Reference Address. If bit posi-
tion 10 of any instruction in a trap or interrupt location
contains a 0, bits 12-31 of that instruction are used as
a 20-bit reference address. This 20-bit reference ad-
di-c55 Cuii be ,li0difie:d vii~,- by \,;:;;ii9 ;iid;~~ct Gddr~~:;
ing. This 20-bit reference address cannot be indexed
or mapped. (See IIInterrupt and Trap Entry Addressing",
later in this chapter.)
4. Direct Reference Address. If neither indirect address-
ing nor indexing is called for by the instruction (i.e.,
if bit 0 and the X field contain zero), the reference
address of the instruction (as defined above) becomes
the effective virtual address. Direct addressing may
be used during real, virtual, or real extended address-
ing modes, including trap and interrupt operations. Di-
rect addressing during virtual addressing does not pre-
clude memory mapping.
5. Indirect Reference Address. The 7-bit operation code
field of the instruction word format provides for as many
as 128 instruction operation codes, nearly all of which
can use indirect addressing (except immediate-operand
and byte-string instructions). If the instruction calls
for indirect addressing (bit position 0 contains a 1), the
reference address (as defined above) is used to access a
word
location that contains the direct reference address
in
bit positions 15-31, or bit positions 12-31 for certain
real extended addressing operations. The indirect ad-
dressing operation is limited to one level, regardless of
the contents of the word location pointed to by the ref-
erence address field of the instruction. Indirect ad-
dressing occurs before indexing; that is, the 17-bit
Main Memory 17

Xerox 550 Specifications

General

Brand	Xerox
Model	550
Category	Printer
Language	English