Bit positions 16 through
31
of
register
R
are
treated
as a
signed
integer,
with
negative
integers
in
two's
complement
form (i.
e.,
a
fixed-point
halfword). The modifier is
alge-
braically
added
to the
top-of-stack
address,
subtracted
from the
space
count,
and
added
to
the
word
count
in the
stack
pointer
doubleword. If, as a result of MSP,
either
the
space
count
or
the
word
count
would be
decreased
be-
low
0
or
increased
above
2
15
_1, the instruction is
aborted.
Then,
the
basic
processor
either
traps to
location
X'42'
or
sets
the
condition code to
reflect
the
reason for
aborting,
depending on
the
stack limit
trap
inhibits.
If the modification
of
the
stack
pointer
doubleword
can
be
successfully performed,
MSP
operates
as follows:
1.
The modifier in register R is
algebraica"y
added
to the
current
top-of-stack
address (SPD15-31)t, to
point
to
a new
top-of-stack
location.
(If the modifier
is
neg-
ative,
it
is
extended
to 17 bits by
appending
a
high-
order
1.)
2.
The
modifier is
algebraica"y
subtracted
from the
cur-
rent
space
count
(SPD33-47) and the result becomes
the new
space
count.
3. The modifier
is
algebraically
added
to the
current
word
count
(SPD49-63) and the result becomes the new
word
count.
4. The condition
code
is
set
to
reflect
the new status
of
the new
space
count
and new word
count.
Affected:
(SPD), CC Trap: Push-down
stack
limit
(SPD)15_31 +
(R)16_31SE-
SPD
15_31
t
(SPD)33_47
- (R)16-31 -
SPD
33
_
47
(SPD)49_63 +
(R)16-31-
SPD
49-63
Condition
code
settings:
2 3 4 Result
of
MSP
o 0 0 0 Space
count>
0,
word
count>
O.
000
Space
count>
0,
word
count
=
O.
o
o
o 0
Space
count
=
0,
word
count>
O.
o
Space
count
= 0,
word
count
= 0,
__
...1:&:
~~
-
()
I.'VU"
I ~I -
v.
Instruction completed
t For real
extended
mode of addressing
this
is a
20-bit
field (12-31); for
real
and virtual addressing modes
it
is a
17-bit
field (15-31).
84
Push- Down Instructions (Privi leged)
If
CC 1,
or
CC3,
or
both CC 1 and CC3
are
l's
after
execution
of
MSP,
the
instruction was
aborted
but
the
push-
down
stack
limit
trap
was
inhibited
by
the
trap-on-space
inhibit
(SPD32), by the
trap-on-word
inhibit
(SPD4S),
or
both. The
condition
code
is
set
to
reflect
the
reason for
aborting
as
follows:
2 3
4 Status
of
space
and
word counts
o Word
count>
O.
Word
count
=
O.
- - 0 - 0
~
word
count
+ modifier
~
2
15
_1.
- Word
count
+ modifier <
0,
and
TW
= 1 or
word
count
+
modi
fi
er
> 2
15
_1, and
TW
=
1.
- 0 - -
Space
count>
O.
- -
Space
count
=
O.
o - - -
0~spacecount-modifier<215_1.
-
Space
count
- modifier <
0,
and
TS
= 1
or
space
count
-
modifier>
2
15
_1,
and
TS
= 1.
PUSH-DOWN
INSTRUCTIONS
(PRIVILEGED)
The computer has two privi leged push-down instructions:
PUSH
STATUS
(PSS)
and
PULL
STATUS
(PLS). These two
in-
structions
and
a Status
Stack
Pointer Doubleword foci
litate
the storing (pushing)
or
loading (pulling)
of
a
particular
environment (contents
of
16
general
registers and Program
Status
Words)
into
or
out
of
a memory
stack.
STATUS
STACK
POINTER
DOUBLEWORD
The Status
Stack
Pointer Doubleword (SSPD) always resides
:r.
rce!
rn6iiiCi}l locations 0
and
1
and
is
dedicated
for
PSS
and
PLS
instructions. The format
of
parameters
contained
within
the Status
Stack
Pointer Doubleword
are
as follows:
Real Memory Location
0:
Real Memory Location 1:
TOP
OF
STACK
ADDRESS
The
Top
of
Stack
Address
(TSA)
is always a
20-bit
real mem-
ory word address and
is
never
mapped. Depending upon
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