Xerox 550 User Manual

NONALLOWED OPERATION TRAP DURING EXECUTION
OF BRANCH INSTRUCTION
The next instruction after a branch instruction may reside
in two possible places: the location following the branch
instruction or a location designated by the branch instruc-
tion. Either of these two locations may be in a protected
memory region or in a region that is physically nonexistent.
The execution of the branch does not cause a trap un less
the instruction that is actually to follow the branch instruc-
tion is in a protected or nonexistent memory region. Traps
do not occur because of any anticipation on the part of the
hardware.
A nonallowed operation trap condition during execution of
a branch instruction wi II occur for the following reasons:
1. The branch instruction is indirectly addressed and the
branch conditions are satisfied, but the address of the
location containing the direct address is either non-
existent or unavai lable for read access to the program
in the slave mode.
2. The branch instruction is unconditional (or the branch
is conditional and the condition for the branch is satis-
fied), but the effective address of the branch instruc-
tion is either nonexistent or unavai lable for instruction
or read access to the program (in slave or master-
protected mode).
If either of the above situations occurs, the basic processor
aborts execution of the branch instruction and executes a
nonallowed operation trap.
Prior to the time that an instruction is accessed from mem-
ory for execution, bit positions 15-31 of the program status
words contain the virtual address of the instruction, referred
to as the instruction address. At this time, the basic pro-
cessor traps to location X
'
40
'
if the actual address of the
instruction is nonexistent or instruction-access protected,
If the instruction address is existent and is not instruction-
access protected, the instruction is accessed and the in-
struction address portion of the program status words is
incremented by 1, so that it now contains the virtual address
of the next instruction in sequence (referred to as the up-
dated instruction address).
If a trap condition occurs during the execution sequence of
any instruction, the basi c processor decrements the updated
instruction address by 1 and then traps to the location as-
signed to the trap condition. If neither a trap condition
r10r a satisfied branch condition occurs during the eXecutiOI'
of an instruction, the next instruction is accessed from the
location Pointed to by the updated instruction address. If
a
satisfied branch condition occurs during the execution of
a branch instruction (and no trap condition occurs), the
next instruction is accessed from the location pointed to by
the effective address of the branch instruction.
90 Execute/Branch Instructions
In the real extended addressing mode, a 20-bit address may
be used as a branch address via indexing or indirect ad-
dressing. If such a branch address, (A), is beyond the first
128K
of real memory, the instruction at (A) will be executed,
but the next instruction address will be (A+l) in the original
128K block unless (A) contains a branch instruction. Note
that with this exception all instructions executed in the
real extended addressing mode must lie in the first 128K of
rea I memory.
EXU EXECUTE
(word
index alignment)
EXECUTE causes the basic processor to access the instruction
in the location pointed to by the effective address of EXU
and execute the subject instruction. The execution of the
subject instruction, including the processing of trap and
interrupt conditions, is performed exactly as if the subject
instruction were initially accessed instead of the EXU in-
struction. If the subject instruction is another EXU, the
basic processor executes the subject instruction pointed to
by the effective address of the second EXU as described
above. Such "chains" of EXECUTE instructions may be of
any length, and are processed (without affecting the updated
instruction address) until an instruction other than EXU is
encountered. After the final subject instruction is executed,
instruction execution proceeds with the next instruction in
sequence after the initial EXU (unless the subject instruc-
tion is an LPSD or XPSD instruction, or is a branch instruc-
tion and the branch condition is satisfied).
If an interrupt activation occurs between the beginning of
an EXU instruction (or chain of EXU instructions) and the
last interruptible point in the subject instruction, the BP
processes the interrupt-servicing routine for the active
interrupt level and then returns program control to the EXU
instruction (or the initio! instruct:cn of a chain of EXU
instructions), which is started anew. Note that a program
is
interruptible after every instruction access, including ac-
cesses made with the EXU instruction, and the interrupt-
ibi lity of the subject instruction is the same as the normal
interruptibility for that instruction.
If a trap condition occurs between the beg inn ing of an EXU
instruction (or chain of EXU instructions) and the comple-
tion of the subject instruction, the basic processor traps to
the appropriate trap location. The instruction address stored
by the XPSD instruction in the trap location is the address
of the EXU instruction (or the initial instruction of a chain
of EXU instructions).
Affected: Determined by
subject instruction
Traps: Determined by
subject instruction
Condition code settings: Determined by subject instruction.

Xerox 550 Specifications

General

Brand	Xerox
Model	550
Category	Printer
Language	English