Xerox 550 User Manual

1st Priority
2nd Priority
3rd Priority
Internal
External
Counter-
Override
Override
Equals-Zero
Interrupts
Interrupts
Interrupts
4th Priority
5th Priority
6th Priority
External
External
I/o Interrupts
Group 2
Group 4
Interrupts
Interrupts
7th Priority
External
Group 5
Interrupts
Figure
11. Interrupt Priority Chain
Internal Override Group (Locations X
I
52
1
through X
I
571).
The six interrupt levels of this group always have the highest
priority in
the system. The four count-pulse interrupt levels
are triggered by pulses from clock sources. Counter 4 has
a
constant frequency of 500 Hz. Counters 1, 2, and 3 can
be individua IIy set to any of four manually switchable fre-
quencies - the commercial line frequency, 500 Hz, 2000 Hz,
or a user-supplied external signal - that may be different
for each counter. Each of the count pulse interrupt loca-
tions must contain one of the modify and test instructions
(MTB, MTH, or MTW), an XPSD, or a PSS instruction.
When the modification (of the effective byte, halfword, or
word) causes a
zero result, the appropriate counter-equals-
zero interrupt level (see IICounter-Equals-Zero Groupll) is
triggered.
Note: Count pulse interrupt level 4 is a subjective time
counter with the following special attribute: When
the
instruction in location X 155
1
is executed as the
result of an interrupt, it must be an MTB, MTH, or
MTW; otherwise, an instruction exception trap
(X
I
40
I
)
will occur.
The internal override group also contains a processor fault
and a memory fault interrupt level. Both locations norma lIy
contain an XPSD or a PSS instruction. The processor fault
interrupt level is triggered by a signal when certain fault
conditions are detected. A POLR instruction must be used
to reset
the fault. The memory fault interrupt level is
34 Centralized Interrupts
triggered by a signal that the memory generates when it
detects certain fault conditions. An LMS instruction must
be used to reset the fault. (See IITrap System
ll
later in
this
chapter for further information on processor and memory
faults.)
Counter-Equals-Zero Group (Locations X 158
1
through X 15B
I
).
Each interrupt level in the counter-equa Is-zero group is as-
sociated with a corresponding count-pulse interrupt level in
the internal override group. When the execution of a mod-
ify
and test instruction in the count-pulse interrupt location
causes a zero result in the effective byte, halfword, or word
location, the corresponding counter-equals-zero interrupt
level is triggered. The counter-equals-zero interrupt loca-
tions normally cO':!tain an XPSD or a PSS instruction and
they
can be inhibited or permitted as a group. If bit 37
(CI) of
the current PSW contains a zero, the counter-equals-
zero interrupt levels are allowed to interrupt the program
being executed. If the CI bit contains a one, the counter-
equals-zero interrupt levels are inhibited from being allowed
to interrupt the program. These interrupt levels wait until
the CI bit is reset to zero and then interrupt the program ac-
cording to priority.
Input/Output Group (Locations X
I
5C through X
I
5FI). This
interrupt group comprises the input/output (I/O) interrupt
level, the control panel interrupt level, and two levels re-
served for future use. The I/O interrupt level accepts inter-
rupt signals from the I/O system. The I/O interrupt location

Xerox 550 Specifications

General

Brand	Xerox
Model	550
Category	Printer
Language	English