EasyManuals Logo
Home>Xilinx>Motherboard>KC705

Xilinx KC705 User Manual

Xilinx KC705
117 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Page #19 background imageLoading...
Page #19 background image
KC705 Evaluation Board 19
UG810 (v1.8) March 20, 2018 www.xilinx.com
Chapter 1: KC705 Evaluation Board Features
User Guide (UG586) [Ref 3]. The KC705 DDR3 SODIMM interface is a 40Ω impedance
implementation. Other memory interface details are available in UG586 and 7SeriesFPGAs
Memory Resources User Guide (UG473) [Ref 4] . For more information about the Micron
MT8JTF12864HZ-1G6G1 part, see [Ref 5].
Linear BPI Flash Memory
[Figure 1-2, callout 3]
The Linear BPI flash memory located at U58 provides 128 MB of nonvolatile storage that
can be used for configuration or software storage. The data, address, and control signals
are connected to the FPGA. The BPI flash memory device is packaged in a 64-pin BGA.
Part number: PC28F00AP30TF (Micron)
Supply voltage: 2.5V
Datapath width: 16 bits (26 address lines and 7 control signals)
Data rate: Up to 33 MHz
The Linear BPI flash memory can synchronously configure the FPGA in Master BPI mode at
the 33 MHz data rate supported by the PC28F00AP30TF flash memory by using a
configuration bitstream generated with BitGen options for synchronous configuration and
for configuration clock division. The fastest configuration method uses the external 66 MHz
oscillator connected to the FPGA EMCCLK pin with a bitstream that has been built to divide
the configuration clock by two. The division is necessary to remain within the synchronous
read timing specifications of the flash memory.
Multiple bitstreams can be stored in the Linear BPI flash memory. The two most significant
address bits (A25, A24) of the flash memory are connected to DIP switch SW13 positions 1
and 2 respectively, and to the RS1 and RS0 pins of the FPGA. By placing valid XC7K325T
bitstreams at four different offset addresses in the flash memory, 1 of the 4 bitstreams can
be selected to configure the FPGA by appropriately setting the DIP switch SW13. The
connections between the BPI flash memory and the FPGA are listed in Table 1-5.
Table 1-5: BPI Flash Memory Connections to the FPGA
U1 FPGA Pin Net Name I/O Standard
U58 BPI Flash Memory
Pin Number Pin Name
W22 FLASH_A0 LVCMOS25 A1 A1
W21 FLASH_A1 LVCMOS25 B1 A2
V24 FLASH_A2 LVCMOS25 C1 A3
U24 FLASH_A3 LVCMOS25 D1 A4
V22 FLASH_A4 LVCMOS25 D2 A5
V21 FLASH_A5 LVCMOS25 A2 A6
Send Feedback

Table of Contents

Other manuals for Xilinx KC705

Questions and Answers:

Question and Answer IconNeed help?

Do you have a question about the Xilinx KC705 and is the answer not in the manual?

Xilinx KC705 Specifications

General IconGeneral
BrandXilinx
ModelKC705
CategoryMotherboard
LanguageEnglish

Related product manuals