Name: Xilinx KC705
Brand: Xilinx
Rating: 5 (1 reviews)

To Next Page

To Previous Page

KC705 Evaluation Board 34

UG810 (v1.8) March 20, 2018 www.xilinx.com

Chapter 1: KC705 Evaluation Board Features

The GTX transceivers in 7 series FPGAs are grouped into four channels described as Quads.

The reference clock for a Quad can be sourced from the Quad above or Quad below the GTX

Quad of interest. There are four GTX Quads on the KC705 board with connectivity as shown

here:

• Quad 115:

Contains 4 GTX transceivers for PCI Express lanes 4-7

MGTREFCLK1 - PCIE_CLK from P1

• Quad 116:

MGTREFCLK0 - Si5326 jitter attenuator

MGTREFCLK1 - FMC LPC GBT clock 0

Contains 4 GTX transceivers for PCIe lanes 0-3

• Quad 117:

MGTREFCLK0 - SGMII clock

MGTREFCLK1 - SMA clock

Contains 4 GTX transceivers with one allocated for: SMA, SGMII, SFP, and FMC LPC

(DP0)

• Quad 118:

MGTREFCLK0 - FMC HPC GBT clock 0

MGTREFCLK1 - FMC HPC GBT clock 1

Contains 4 GTX transceivers for FMC HPC (DP0 - DP3)

Table 1-10 lists the GTX interface connections to the FPGA (U1).

Table 1-10: GTX Interface Connections for FPGA U1

Transceiver Bank Associated Net Name Connections

MGT_BANK_115 GTXE2_CHANNEL_X0Y0 PCIe7

GTXE2_CHANNEL_X0Y1 PCIe6

GTXE2_CHANNEL_X0Y2 PCIe5

GTXE2_CHANNEL_X0Y3 PCIe4

MGTREFCLK0 N/C

MGTREFCLK1 PCIe_CLK

Send Feedback

Xilinx KC705 User Manual

Other manuals for Xilinx KC705