KC705 Evaluation Board 38
UG810 (v1.8) March 20, 2018 www.xilinx.com
Chapter 1: KC705 Evaluation Board Features
Table 1-12 lists the PCIe edge connector connections for Quad 115.
PCIE_TX5_P U4 A39 PERp5 Integrated Endpoint block
transmit pair
GTXE2_CHANNEL_X0Y2
PCIE_TX5_N U3 A40 PERn5 Integrated Endpoint block
transmit pair
GTXE2_CHANNEL_X0Y2
PCIE_TX6_P V2 A43 PERp6 Integrated Endpoint block
transmit pair
GTXE2_CHANNEL_X0Y1
PCIE_TX6_N V1 A44 PERn6 Integrated Endpoint block
transmit pair
GTXE2_CHANNEL_X0Y1
PCIE_TX7_P Y2 A47 PERp7 Integrated Endpoint block
transmit pair
GTXE2_CHANNEL_X0Y0
PCIE_TX7_N Y1 A48 PERn7 Integrated Endpoint block
transmit pair
GTXE2_CHANNEL_X0Y0
PCIE_CLK_QO_P U8 A13 REFCLK+ Integrated Endpoint block
differential clock pair from
PCIe
MGT_BANK_115
PCIE_CLK_QO_N U7 A14 REFCLK- Integrated Endpoint block
differential clock pair from
PCIe
MGT_BANK_115
PCIE_PRSNT_B J32 2, 4, 6 A1 PRSNT#1 J42 Lane Size Select jumper N/A
PCIE_WAKE_B F23 B11 WAKE# Integrated Endpoint block
wake signal, not connected
on KC705 board
N/A
PCIE_PERST_B G25 A11 PERST Integrated Endpoint block
reset signal
N/A
Table 1-11: PCIe Edge Connector Connections (Cont’d)
Schematic Net
Name
FPGA Pin
(U1)
PCIe Edge
Connector
Pin
PCIe Edge
Pin Name
Function FFG900 Placement
Table 1-12: GTX Quad 115 PCIe Edge Connector Connections
Quad 115 Pin Name
FPGA
Pin (U1)
Schematic Net Name
PCIe Edge
Connector
Pin
PCIe Edge
Pin Name
FFG900 Placement
MGTXTXP0_115_Y2 Y2 PCIE_TX7_P A47 PERp7 GTXE2_CHANNEL_X0Y0
MGTXTXN0_115_Y1 Y1 PCIE_TX7_N A48 PERn7 GTXE2_CHANNEL_X0Y0
MGTXRXP0_115_AA4 AA4 PCIE_RX7_P B45 PETp7 GTXE2_CHANNEL_X0Y0
MGTXRXN0_115_AA3 AA3 PCIE_RX7_N B46 PETn7 GTXE2_CHANNEL_X0Y0
MGTXTXP1_115_V2 V2 PCIE_TX6_P A43 PERp6 GTXE2_CHANNEL_X0Y1
MGTXTXN1_115_V1 V1 PCIE_TX6_N A44 PERn6 GTXE2_CHANNEL_X0Y1
MGTXRXP1_115_Y6 Y6 PCIE_RX6_P B41 PETp6 GTXE2_CHANNEL_X0Y1
MGTXRXN1_115_Y5 Y5 PCIE_RX6_N B42 PETn6 GTXE2_CHANNEL_X0Y1
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