KC705 Evaluation Board 63
UG810 (v1.8) March 20, 2018 www.xilinx.com
Chapter 1: KC705 Evaluation Board Features
FPGA Mezzanine Card Interface
[Figure 1-2, callout 30 - 31]
The KC705 evaluation board for the Kintex-7 FPGA supports the VITA 57.1 FPGA Mezzanine
Card (FMC) specification by providing subset implementations of a high pin count (HPC)
connector at J22 and a low pin count (LPC) connector at J2. Both connectors use the same
10 x 40 form factor, except the HPC version is fully populated with 400 pins and the LPC
version is partially populated with 160 pins. Both connectors are keyed so that a the
mezzanine card faces away from the KC705 board when connected.
Signaling Speed Ratings:
• Single-ended: 9 GHz (18 Gb/s)
• Differential Optimal Vertical: 9 GHz (18 Gb/s)
• Differential Optimal Horizontal: 16 GHz (32 Gb/s)
• High Density Vertical: 7 GHz (15 Gb/s)
The Samtec connector system is rated for signaling speeds up to 9 GHz (18 Gb/s) based on
a -3 dB insertion loss point within a two-level signaling environment.
Connector Type:
• Samtec SEAF Series, 1.27 mm (0.050 in) pitch. Mates with SEAM series connector
For more information about SEAF series connectors see [Ref 19].
HPC Connector J22
[Figure 1-2, callout 30]
The 400-pin HPC connector defined by the FMC specification (Figure B-1, page 86)
provides connectivity for up to:
• 160 single-ended or 80 differential user-defined signals
• 10 GTX transceivers
•2 GTX clocks
• 4 differential clocks
• 159 ground and 15 power connections
The connections between the HPC connector at J22 and FPGA U1 (Table 1-28) implement a
subset of this connectivity:
• 58 differential user defined pairs
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