Xilinx KC705 User Manual

KC705 Evaluation Board 69
UG810 (v1.8) March 20, 2018 www.xilinx.com
Chapter 1: KC705 Evaluation Board Features
• 2 differential clocks
• 61 ground and 9 power connections
Table 1-29: LPC Connections, J2 to FPGA U1
J2 Pin Schematic Net Name
I/O
Standard
U1
FPGA
Pin
J2
Pin
Schematic Net Name
I/O
Standard
U1
FPGA
Pin
C2 FMC_LPC_DP0_C2M_P F2 D1 PWRCTL1_VCC4A_PG
C3 FMC_LPC_DP0_C2M_N F1 D4 FMC_LPC_GBTCLK0_M2C_P LVDS N8
C6 FMC_LPC_DP0_M2C_P F6 D5 FMC_LPC_GBTCLK0_M2C_N LVDS N7
C7 FMC_LPC_DP0_M2C_N F5 D8 FMC_LPC_LA01_CC_P LVDS AE23
C10 FMC_LPC_LA06_P LVDS AK20 D9 FMC_LPC_LA01_CC_N LVDS AF23
C11 FMC_LPC_LA06_N LVDS AK21 D11 FMC_LPC_LA05_P LVDS AG22
C14 FMC_LPC_LA10_P LVDS AJ24 D12 FMC_LPC_LA05_N LVDS AH22
C15 FMC_LPC_LA10_N LVDS AK25 D14 FMC_LPC_LA09_P LVDS AK23
C18 FMC_LPC_LA14_P LVDS AD21 D15 FMC_LPC_LA09_N LVDS AK24
C19 FMC_LPC_LA14_N LVDS AE21 D17 FMC_LPC_LA13_P LVDS AB24
C22 FMC_LPC_LA18_CC_P LVDS AD27 D18 FMC_LPC_LA13_N LVDS AC25
C23 FMC_LPC_LA18_CC_N LVDS AD28 D20 FMC_LPC_LA17_CC_P LVDS AB27
C26 FMC_LPC_LA27_P LVDS AJ28 D21 FMC_LPC_LA17_CC_N LVDS AC27
C27 FMC_LPC_LA27_N LVDS AJ29 D23 FMC_LPC_LA23_P LVDS AH26
C30 FMC_LPC_IIC_SCL D24 FMC_LPC_LA23_N LVDS AH27
C31 FMC_LPC_IIC_SDA D26 FMC_LPC_LA26_P LVDS AK29
C34 GA0=0=GND D27 FMC_LPC_LA26_N LVDS AK30
C35 VCC12_P D29 FMC_LPC_TCK_BUF
C37 VCC12_P D30 FMC_HPC_TDO_LPC_TDI
C39 VCC3V3 D31 FMC_LPC_TDO_FPGA_TDI
D32 VCC3V3
D33 FMC_LPC_TMS_BUF
D34 NC
D35 GA1=0=GND
D36 VCC3V3
D38 VCC3V3
D40 VCC3V3
G2 FMC_LPC_CLK1_M2C_P LVDS AG29 H1 NC
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Xilinx KC705 Specifications

General

Brand	Xilinx
Model	KC705
Category	Motherboard
Language	English