Xilinx KC705 User Manual

KC705 Evaluation Board 28
UG810 (v1.8) March 20, 2018 www.xilinx.com
Chapter 1: KC705 Evaluation Board Features
Clock Generation
There are five clock sources available for the FPGA fabric on the KC705 board (refer to
Table 1-8).
Table 1-9 lists the pin-to-pin connections from each clock source to the FPGA.
Table 1-8: KC705 Board Clock Sources
Clock Name Reference Description
System Clock
U6
SiT9102 2.5V LVDS 200 MHz Fixed Frequency Oscillator (Si Time). See
System Clock Source, page 29.
User Clock
U45
Si570 3.3V LVDS I2C Programmable Oscillator
(Silicon Labs). Default power-on frequency 156.250 MHz. See
Programmable User Clock Source, page 29.
User SMA Clock
(differential pair)
J11
USER_SMA_CLOCK_P (net name).
See User SMA Clock Input, page 30.
J12
USER_SMA_CLOCK_N (net name)
See User SMA Clock Input, page 30
GTX SMA REF Clock
(differential pair)
J16
SMA_MGT_REFCLK_P (net name).
See GTX SMA Clock Input, page 31.
J15
SMA_MGT_REFCLK_N (net name).
See GTX SMA Clock Input, page 31.
Jitter Attenuated
Clock
U70
Si5324C LVDS precision clock multiplier/jitter attenuator (Silicon
Labs).
See Jitter Attenuated Clock, page 32.
Table 1-9: Clock Source to FPGA U1 Connections
Clock Source Pin Schematic Net Name I/O Standard U1 FPGA Pin
U6.5 SYSCLK_N LVDS AD11
U6.4 SYSCLK_P LVDS AD12
U45.5 USER_CLOCK_N LVDS_25 K29
U45.4 USER_CLOCK_P LVDS_25 K28
J12.1 USER_SMA_CLOCK_N LVDS_25 K25
J11.1 USER_SMA_CLOCK_P LVDS_25 L25
J15.1 SMA_MGT_REFCLK_N N/A (MGT REFCLK INPUT) J7
J16.1 SMA_MGT_REFCLK_P N/A (MGT REFCLK INPUT) J8
U70.29 Si5326_OUT_N N/A (MGT REFCLK INPUT) L7
U70.28 Si5326_OUT_P N/A (MGT REFCLK INPUT) L8
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Xilinx KC705 Specifications

General

Brand	Xilinx
Model	KC705
Category	Motherboard
Language	English