106
Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
VccSus5) will always be powered up before VccSus3_3 and thus circuitry to satisfy the sequence
requirement is not needed. However, in platforms that do not derive the VccSus3_3 rail from the
VccSus5 rail, this rule must be observed in the platform design as described above. See Figure 50.
4.7.2.2 3.3V/1.5V Power Sequencing
The Intel
®
6300ESB has power sequencing requirements for the 3.3 V and 1. 5V rails in respect to
each other. This requirement is as follows: The 3.3 V and 1.5 V rails must power up or down
simultaneously. When I/O pads are powered by the 3.3 V rail before the core is powered by the 1.5
V rail, a current spike anomaly will be observed.
4.7.3 PCI-X Power Sequencing
The 1.5 V voltage must be valid before the first CLK66 pulse is driven into the 6300ESB ICH. This
can be guaranteed by gating the CK409 clocks using a power good signal from the 1.5V regulator.
When the first CLK66 pulse is driven before 1.5V is valid, the PCI-X PLL may fail to correctly
lock.
4.7.4 DDR Memory Power Sequencing Requirements
No DDR-SDRAM power sequencing requirements are specified during power up or power down if
the following criteria are met:
• VDD and VDDQ to memory devices are driven from a single power converter output.
• VTT is limited to 1.44 V (reflecting VDDQ(max)/2 + 50 mV VREF variation + 40 mV VTT
variation).
• VREF tracks VDDQ/2.
• A minimum resistance of 42 Ω (22 Ω series resistor + 22 Ω parallel resistor ± 5 percent
tolerance) limits the input current from the VTT supply into any pin.
Figure 50. Example V
5REF/
3.3 V Sequencing Circuitry
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