January 2007 143
Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
System Memory Design Guidelines (DDR-SDRAM)
The command signals shall be routed using a 2:1 trace spacing to trace width ratio for signals
within the DDR group, except clocks and strobes. Command signals shall be routed on inner layers
with minimized external traces.
5.4.6.2 Command Topology Routing Guidelines
Table 38 presents the command topology routing guidelines.
Figure 71. Command Routing for Topology
w
DIMM1 PAD
DIMM0 PAD
MCH
P1
L3
L2
Rt
MCH
Pin
L1
Table 38. Command Topology Routing Guidelines (Sheet 1 of 2)
Parameter Routing Guidelines
Signal Group SMA[12:6,3,0], SBA[1:0], SRAS#, SCAS#, SWE#
Motherboard Topology Daisy-Chain with Parallel Termination
Reference Plane Ground Referenced
Characteristic Trace Impedance (Zo) 55
Ω ±15%
Nominal Trace Width Inner layers: 4 mils
Outer layers: 5 mils
Minimum Spacing to Trace Width Ratio 2:1 (e.g., 8 mil space to 4 mil trace)
Minimum Isolation Spacing to non-DDR Signals 20 mils
Package Length P1 500 mils ± 250 mils
Refer to Table 39 for exact package lengths.
Trace Length P1+ L1 Min = 2.0 inches
Max = 5.5 inches
Trace Length P1+ L1+L2+L3 Max = 7.5 inches
Trace Length L2 – Total DIMM to DIMM spacing Max = 2.0 inches
Trace Length L3 – Second DIMM Pad to Parallel
Resistor Pad
Max = 1.5 inches
NOTES:
1. Recommended resistor values and trace lengths may change in a later revision of the design guide.
2. Power distribution vias from Rt to Vtt are not included in this count.
3. The overall maximum and minimum length to the DIMM must comply with clock length matching
requirements.
4. It is possible to route using three vias if one via is shared that connects to the DIMM1 pad and parallel
termination resistor.
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