Intel 855GME User Manual (English)

Name: Intel 855GME
Brand: Intel
Rating: 4 (1 reviews)

Intel ® Pentium ® M/Celeron ® M Processor FSB Design and Power Delivery Guidelines37
Intel ® Pentium ® M/Celeron ® M Processor FSB Design Recommendations37
- Recommended Stack-Up Routing and Spacing Assumptions37
Three-To-One Trace Spacing-To-Trace Width Example38
- Signal Propagation Time-To-Distance Relationship and Assumptions39
Trace Spacing Versus Trace to Reference Plane Example38
Two-To-One Trace Spacing-To-Trace Width Example38
Recommended Stack-Up Capacitive Coupling Model39
- Common Clock Signals40
- Common Clock Signal Internal Layer Routing Guidelines40
  - Package Length Compensation41
  - Source Synchronous Signals General Routing Guidelines42
Common Clock Topology42
- Signal Package Lengths and Minimum Board Trace Lengths42
- Signals GND Referencing to Layer 5 and Layer 7 Ground Planes43
- Data Signals44
- Source Synchronous Address Signals45
- Signals GND Referencing to Layer 2 and Layer 4 Ground Planes46
- Data Signals46
  - Source Synchronous - Data Group47
- Address Signals47
  - Source Synchronous - Address Group48
- Trace Length Mismatch Mapping48
- Data Signal Routing Guidelines48
  - GMCH (82855GME) FSB Signal Package Lengths49
  - Intel ® Pentium ® M/Celeron ® M Processor and Intel ® 855GME Chipset49
- Signal Trace Length Mismatch Mapping49
- Address Signal Routing Guidelines49
- FSB Signal Package Lengths50
Trace Length Equalization Procedures with Allegro57
- Asynchronous Signals58
Asynchronous AGTL+ Nets58
- Topology 1A: Open Drain (OD) Signals Driven by the Intel Pentium M/Celeron M Processor - IERR59
- Topology 1B: Open Drain (OD) Signals Driven by the Intel Pentium M/Celeron M Processor - FERR# and THERMTRIP59
Layout Recommendations for Topology 1A59
- Topology 1C: Open Drain (OD) Signals Driven by the Intel Pentium M/Celeron M Processor - PROCHOT60
Routing Illustration for Topology 1A59
Layout Recommendations for Topology 1B60
- Topology 2A: Open Drain (OD) Signals Driven by and Gate-PWRGOOD61
Routing Illustration for Topology 1B60
Layout Recommendations for Topology 1C61
- Topology 2B: CMOS Signals Driven by 6300ESB-LINT0/INTR, LINT1/NMI, A20M#, IGNNE#, SLP#, SMI#, and STPCLK62
- Topology 3: CMOS Signals Driven by 6300ESB to CPU and FWH - INIT62
Routing Illustration for Topology 1C61
Routing Illustration for Topology 2A61
Layout Recommendations for Topology 2A62
Layout Recommendations for Topology 2B62
- Voltage Translation Logic63
- Pentium ® M/Celeron ® M Processor RESET# Signal64
Routing Illustration for Topology 2B62
Processor RESET# Signal Routing Topology with no ITP700FLEX Connector64
- Processor RESET# Routing Example65
Voltage Translation Circuit64
Processor RESET# Signal Routing Example with ITP700FLEX Debug Port65
Processor RESET# Signal Routing Guidelines with ITP700FLEX Connector65
- Pentium ® M/Celeron ® M Processor and Intel 855GME66
  - Chipset GMCH (82855GME) Host Clock Signals66
- Pentium ® M/Celeron ® M Processor)66
  - Routing Recommendations67
- (82855GME) Host Clock Layout Routing Example67
- AGTL+ I/O Buffer Compensation69
- Pentium ® M/Celeron ® M Processor AGTL+ I/O Buffer Compensation69
- Resistive Compensation70
- Primary Side Layout71
- Pentium ® M/Celeron ® M Processor System Bus Strapping72
  - Design Recommendations74
- PLL Voltage Design for Low Voltage Intel74
  - Pentium ® M74
  - Processors on 90 Nm Process with 2 MB L2 Cache74
Processor RESET# Signal Routing Topology with ITP700FLEX Connector65
Intel System Validation Debug Support75
- ITP Support75
- Intel ® Pentium ® M/Celeron ® M Processor On-Die Logic76
  - Analyzer Trigger (ODLAT) Support76
Onboard Debug Port Routing Guidelines77
- Recommended Onboard ITP700FLEX Implementation77
  - ITP Signal Routing Guidelines77
ITP700FLEX Debug Port Signals78
- Pentium M/Celeron M Processor80
Recommended ITP700FLEX Signal Terminations80
- ITP Signal Routing Example81
- ITP_CLK Routing to ITP700FLEX Connector82
- ITP700FLEX Design Guidelines for Production Systems83
- Recommended ITP Interposer Debug Port Implementation84
  - ITP_CLK Routing to ITP Interposer84
  - ITP Interposer Design Guidelines for Production Systems85
- Logic Analyzer Interface (LAI)85
  - Electrical Considerations86
  - Mechanical Considerations86
- Processor Phase Lock Loop (PLL) Design Guidelines86
  - Processor PLL Power Delivery86
- Power Delivery and Decoupling87
  - Processor PLL Decoupling Requirements88
  - Processor PLL Voltage Supply Power Sequencing88
- Routing Example88
- Thermal Power Dissipation89
- Intel ® Pentium ® M/Celeron ® M Processor Decoupling Recommendations90
Intel ® Pentium ® M/Celeron ® M Processor Socket Core Power Delivery Corridor92
Intel ® Pentium ® M/Celeron ® M Processor Core Power Delivery93
- North Corridor' Zoom-In View99
  - Processor and GMCH VCCP Voltage Plane and Decoupling100
  - GMCH Core Voltage Plane and Decoupling101
- Power and Sleep State Definitions101
- Power Delivery Map103
- Intel 855GME Chipset Platform Power-Up Sequence105
- Intel 855GME Chipset Platform Power Delivery Guidelines107
  - GMCH VCCSM Decoupling108
  - Intel 855GME Chipset and Decoupling Guidelines108
Intel ® Pentium ® M/Celeron ® M Processor Core Power Delivery and Decoupling Concept Example (Option #4)93
GMCH Decoupling Recommendations108
- DDR SDRAM VDD Decoupling109
- DDR VTT Decoupling Placement and Layout Guidelines109
- DDR Memory Power Delivery Design Guidelines109
GMCH System Memory Reference Voltage Generation Circuit112
- Other GMCH Reference Voltage and Analog Power Delivery113
- Thermal Design Power121
Power Signal Decoupling121

System Memory Design Guidelines (DDR-SDRAM)123

Integrated Graphics Display Port153

AGP Port Design Guidelines173

Hub Interface183

Intel ® 6300ESB Design Guidelines191

Miscellaneous Logic247

Platform Clock Routing Guidelines249

Schematic Checklist Summary265

Layout Checklist299

Intel 855GME User Manual

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Brand	Intel
Model	855GME
Category	Computer Hardware
Language	English