58
Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
Intel
®
Pentium
®
M/Celeron
®
M Processor FSB Design and Power Delivery Guidelines
4.1.5 Asynchronous Signals
The following sections describe the topologies and layout recommendations for the asynchronous
open drain and CMOS signals found on the platform. All open drain signals listed in the following
sections must be pulled-up to VCCP (1.05 V). When any of these open drain signals are pulled-up
to a voltage higher than VCCP, the reliability and power consumption of the processor may be
affected. Therefore, it is very important to follow the recommended pull-up voltage for these
signals. All signals must meet the AC and DC specifications as documented in the Intel Pentium
®
M Processor Datasheet, Intel Pentium
®
M Processor on the 90nm Process with 2MB L2 Cache
Datasheet, or the Intel Celeron
®
M Processor Datasheet.
Table 10. Asynchronous AGTL+ Nets
Signal
Names
Description Topology #
CPU I/O
Type
Output
Output
Buffer
Type
Input
Input Power
Well
IERR#
Internal error 1A O CPU AGTL+
System
Receiver
Vcc_Receiver
FERR# Floating point
error
1B O CPU AGTL+ 6300ESB
Main I/O
(3.3 V)
THRMTRIP# Thermal
sensor
1B O CPU AGTL+
System
Receiver
Vcc_Receiver
PROCHOT# Thermal
sensor
1C O CPU AGTL+
System
Receiver
Vcc_Receiver
PWRGOOD System power
good
2A I
AND
Gate
OD
CMOS
CPU N/A
DPSLP#
††
Deep sleep I CPU
LINT0/INTR Local
interrupts
2B I 6300ESB CMOS CPU N/A
LINT1/NMI Local
interrupts
2B I 6300ESB CMOS CPU N/A
SLP# Sleep 2B I 6300ESB CMOS CPU N/A
STPCLK# Processor
stop clock
2B I 6300ESB CMOS CPU N/A
IGNNE# Ignore next
numeric error
2B I 6300ESB CMOS CPU N/A
SMI# System
management
interrupt
2B I 6300ESB CMOS CPU N/A
A20M# Address 20
mask
2B I 6300ESB CMOS CPU N/A
INIT# Processor
initialize
3 I 6300ESB CMOS
CPU,
FWH
N/A, 3.3 V
†† Only supported by ICH4-M device. When not used, pull-up at CPU with 4.7 K
Ω ± 5% resistor at VCCP.
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