Intel 855GME User Manual

272
Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
Schematic Checklist Summary
12.3 Intel
®
855GME Chipset GMCH (82855GME)
Checklist
12.3.1 System Memory
12.3.1.1 GMCH System Memory Interface Checklist
Table 121 presents the GMCH system memory interface checklist. Figure 150 depicts the reference
voltage level for SMVREF.
Table 121. GMCH System Memory Interface Checklist (Sheet 1 of 2)
Pin Name
System
Pull-up/Pull-down
Series
Resistor
Notes
√
SRCVENIN#
This signal shall be routed to a via next to
ball and left as a NC.
SRCVENOUT#
This signal shall be routed to via next to
ball and left as a NC.
SBA[1:0]
56
Ω pull-up to
V_1P25_MEMVTT
Connect to DIMM 0 and DIMM 1.
SCAS#
56
Ω pull-up to
V_1P25_MEMVTT
Connect to DIMM 0 and DIMM 1.
SRAS#
56
Ω pull-up to
V_1P25_MEMVTT
Connect to DIMM 0 and DIMM 1.
SWE#
56
Ω pull-up to
V_1P25_MEMVTT
Connect to DIMM 0 and DIMM 1.
SCKE[1:0]
56
Ω pull-up to
V_1P25_MEMVTT
Connect to DIMM 0
SCKE[3:2]
56
Ω pull-up to
V_1P25_MEMVTT
Connect to DIMM 1
SCS#[1:0]
56
Ω pull-up to
V_1P25_MEMVTT
Connect to DIMM 0
SCS#[3:2]
56
Ω pull-up to
V_1P25_MEMVTT
Connect to DIMM 1
SDQ[63:0]
56
Ω pull-up to
V_1P25_MEMVTT
10
Ω Connect to DIMM 0 and DIMM 1.
SDM[7:0]
56
Ω pull-up to
V_1P25_MEMVTT
10
Ω Connect to DIMM 0 and DIMM 1.
SDQS[7:0]
56
Ω pull-up to
V_1P25_MEMVTT
10
Ω Connect to DIMM 0 and DIMM 1.
SDQ[71:64]
56
Ω pull-up to
V_1P25_MEMVTT
10
Ω
When ECC support is not implemented,
SDQ[71:64], SDM8, and SDQS8 shall be
left as NC. For ECC support, these signals
connect to DIMMs.
SDM8
56
Ω pull-up to
V_1P25_MEMVTT
10
Ω
When ECC support is not implemented,
SDQ[71:64], SDM8, and SDQS8 shall be
left as NC. For ECC support, these signals
connect to DIMMs.

Intel 855GME Specifications

General

Brand	Intel
Model	855GME
Category	Computer Hardware
Language	English