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Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
Intel
®
6300ESB Design Guidelines
9.9 PCI
The 6300ESB provides a PCI Bus interface that is compliant with the PCI Local Bus Specification,
Revision 2.2
. The implementation is optimized for high-performance data streaming when the
6300ESB is acting as either the target or the initiator on the PCI bus. For more information on the
PCI Bus interface, please refer to the
PCI Local Bus Specification, Revision 2.2.
9.9.1 PCI Routing Summary
The following represents a summary of the routing guidelines for the PCI devices. The 6300ESB
supports four PCI devices. Simulations assume that PCI cards follow the
PCI Local Bus
Specification, Revision 2.2
, trace length guidelines.
Note: These routing guidelines are created using the stack-up described in Section 3.1, “Nominal Board
Stack-Up” on page 33.
Table 89. Bus Capacitance Reference Chart
Device
# of Devices/
Trace Length
Capacitance Includes Cap (pF)
6300ESB 1 Pin Capacitance 12
CK409 1 Pin Capacitance 10
DIMMS/RIMMS 2
Pin Capacitance (10 pF) + 1 inch worth of trace
capacitance (2 pF/inch) per DIMM/RIMM and 2 pF
connector capacitance per DIMM/RIMM.
28
3 42
PCI 2
Each PCI add-in card is allowed up to 40 pF + 3 pF per
each connector.
86
3 129
4 172
5 215
SMBus Trace
Length in inches
= 24 2 pF per inch of trace length 48
= 36 72
= 48 96
CNR 1
Pin Capacitance (10 pF) + 6 inch worth of trace
capacitance (2 pF/inch) and 2 pF connector capacitance.
24
Table 90. Bus Capacitance/Pull-Up Resistor Relationship
Physical Bus Segment
Capacitance
Pull-Up Range (For Vcc = 3.3V
0 to 100 pF 8.2K
Ω to 1.2 KΩ
100 to 200 pF 4.7K Ω to 1.2 KΩ
200 to 300 pF 3.3K Ω to 1.2 KΩ
300 to 400 pF 2.2K Ω to 1.2 KΩ
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