Intel 855GME User Manual

January 2007 61
Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
4.1.5.4 Topology 2A: Open Drain (OD) Signals Driven by AND Gate–
PWRGOOD
The Topology 2A OD signal PWRGOOD, which is driven by an AND gate (Intel Pentium
M/Celeron M processor CMOS signal input), shall adhere to the following routing and layout
recommendations. Table 14 lists the recommended routing requirements for the PWRGOOD signal
of the Intel Pentium M/Celeron M processor. The routing guidelines allow the signal to be routed
as either micro-strip or strip-lines using 55 Ω ± 15 percent characteristic trace impedance. The
pull-up voltage for termination resistor Rtt is VCCP (1.05 V). Figure 19 depicts the routing
illustration for Topology 2A.
Note: The output from the AND Gate (AND of power supply PWRGD_3V and CPU VR__PWRGD)
shall be routed point-to-point to the Intel Pentium M/Celeron M processor’s PWRGOOD signal.
The routing from the Intel Pentium M/Celeron M processor’s PWRGOOD pin shall fork out to the
termination resistor, Rtt, and the AND gate. Segments L1 and L2 from Table 14 shall not T-split
from a trace from the Intel Pentium M/Celeron M processor pin.
Figure 18. Routing Illustration for Topology 1C
Table 13. Layout Recommendations for Topology 1C
L1 L2 L3 L4 Rs R1 R2- Rtt
Transmission
Line Type
0.5” – 12.0” 0” – 3.0” 0” – 3.0” 0.5” – 12.0” 330 Ω ± 5% 1.3 kΩ ± 5% 330 Ω ±5% 56Ω ± 5% Micro-strip
0.5” – 12.0” 0” – 3.0” 0” – 3.0” 0.5” – 12.0” 330 Ω ± 5% 1.3 kΩ ± 5% 330 Ω ±5% 56Ω ± 5% Strip-line
CPU
L1
L3
L2
Rs
3.3
3904
3904
L4
3.3
Q1
Q2
R1
R2
V_IO_RCVR
(System
receiver)
VCCP
Rtt
Figure 19. Routing Illustration for Topology 2A
B4871-01
+27
CPU_VR_PWRGD
PWRGD_3V
L1L2
Rtt
VCCP

Intel 855GME Specifications

General

Brand	Intel
Model	855GME
Category	Computer Hardware
Language	English