62
Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
4.1.5.5 Topology 2B: CMOS Signals Driven by 6300ESB-LINT0/INTR,
LINT1/NMI, A20M#, IGNNE#, SLP#, SMI#, and STPCLK#
The Topology 2B CMOS LINT0/INTR, LINT1/NMI, A20M#, IGNNE#, SLP#, SMI#, and
STPCLK# signals shall implement a point-to-point connection between the 6300ESB and the Intel
Pentium M/Celeron M processor. The routing guidelines allow both signals to be routed as either
micro-strip or strip-lines using 55 Ω ± 15 percent characteristic trace impedance. No additional
motherboard components are necessary for this topology. Figure 20 depicts the routing illustration
and Table 15 presents the layout recommendations for Topology 2B.
4.1.5.6 Topology 3: CMOS Signals Driven by 6300ESB
to CPU and FWH – INIT#
The signal INIT# shall adhere to the following routing and layout recommendations. Table 16 lists
the recommended routing requirements for the INIT# signal of the 6300ESB. The routing
guidelines allow both signals to be routed as either micro-strip or strip-lines using 55 Ω ± 15
percent characteristic trace impedance. Figure 21 depicts the recommended implementation for
providing voltage translation between the 6300ESB’s INIT# voltage signaling level and any
firmware hub (FWH) that utilizes a 3.3 V interface voltage (shown as a supply V_IO_FWH). Refer
to Section 4.1.5.7 for more details on the voltage translator circuit. For convenience, the entire
topology and required transistors and resistors for the voltage translator are shown in Figure 21.
Series resistor Rs is a component of the voltage translator logic circuit and serves as a driver
isolation resistor. Rs is shown separated by distance L3 from the first bipolar junction transistor
(BJT), Q1, to emphasize the placement of Rs with respect to Q1. The placement of Rs a distance of
L3 before the Q1 BJT is a specific implementation of the generalized voltage translator circuit
shown in Figure 22. The routing recommendations of transmission line L3 in Figure 21 are listed in
Table 16. Rs must be placed at the beginning of the T-split of the trace from 6300ESB’s INIT# pin.
Table 14. Layout Recommendations for Topology 2A
L1 L2 Rtt Transmission Line Type
0.5” – 12.0” 0” – 3.0” 330 Ω ± 5% Micro-strip
0.5” – 12.0” 0” – 3.0” 330
Ω ±5% Strip-line
Figure 20. Routing Illustration for Topology 2B
Table 15. Layout Recommendations for Topology 2B
L1 Transmission Line Type
0.5” – 12.0” Micro-strip
0.5” – 12.0” Strip-line
CPU
Intel
®
6300ESB
L1
To Next Page
Loading...
Need help?
General
