January 2007 151
Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
System Memory Design Guidelines (DDR-SDRAM)
Note: All three differential clocks per DDR DIMM must be routed and driven to each respective DIMM
connector, regardless of ECC support.
The DRAM Data Integrity Mode (DDIM) bit of the DRC register (Device 0; Offset 7C-7Fh; bit 21)
provides the option to enable or disable ECC operation mode in the GMCH. By default, this bit is
set to ‘0’ and ECC functionality is disabled. In such a case, the SDQ[71:64] and SDQS8 pins of the
GMCH may be left as no connects.
On platforms where ECC memory is supported, it is important that all relevant SDQ and SDQS
signals to the DIMMs be disabled when the system is populated with only non-ECC or a
combination of ECC and non-ECC memory. In such cases, the registers mentioned in the next
section must be programmed appropriately.
5.5.2 DRAM Clock Flexibility
The DRAM Clock Control Disable Register (DCLKDIS: I/O Address 2E-2Fh) and the DRAM
Controller Power Management Control Register, bit 10, (PWRMG: I/O Address 68-6Bh) provides
the capability to enable and disable the CS/CKE and SCK signals to unpopulated DIMMs. The
GMCH provides the flexibility to route any differential clock pair to any SCK clock pair on the
DIMMs provided that the BIOS enables/disables these clocks appropriately (e.g., the GMCH’s
SCK0 pair may be routed either to the DIMM’s SCK0 pair or any other pair such as SCK1 or
SCK2, etc.).
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