RL78/F13, F14 CHAPTER 17 LIN/UART MODULE (RLIN3)
R01UH0368EJ0210 Rev.2.10 1240
Dec 10, 2015
(2) Data Reception
Data reception is performed by using the synchronized LRXDn (an internal signal) that is the input from the LRXDn pin
synchronized with the prescaler clock.
The byte field is synchronized at the falling edge of the start bit for the synchronized LRXDn signal. After the falling edge is
detected, resampling is performed 0.5 Tbits later if the sampling count per 1 Tbit is even and {(sampling count +
1)/2}/(sampling count) Tbits later if odd. If the synchronized LRXDn signal is low, the bit is recognized as a start bit. The bit
is not recognized as a start bit if the LRXDn signal is fixed at low after the reset is cleared or if a high level is detected during
the resampling.
After the start bit is detected, 1 bit is sampled per Tbit.
Note that when the BERE bit in the LEDEn register is set to 1, sampling proceeds at the same time as the detection of a bit
error.
The LIN/UART module has a noise filter function with respect to received data. If the LRDNFS bit in the LMDn register is 0,
the noise filter is used. For a sampling value, the value determined by a 3-sampling majority rule by the prescaler clock is
used. If the LRDNFS bit in the LMDn register is 1, the noise filter is not used. In this case, for a sampling value, the
synchronized LRXDn value at the sampling position is used as is.
Figure 17-37 shows an example of data reception timing.
Figure 17-37. Example of Data Reception Timing (when Sampling Count is 16 in 1 Tbit)
LRXDn
ST D0
D0
D0
D1
D1
D1 D2 D3 D4 D5 D6 D7 SP
LRXDn (Enlarged)
Prescaler clock
(internal signal)
Synchronized LRXDn
(internal signal)
n = 0, 1
Falling edge
detection
Confirmed to be low 0.5 Tbit
after falling edge detection.
Bit 0 is read 1 Tbit after
confirmation of a low level.
After that, data bit is
read every Tbit.
0.5 Tbit 1 Tbit (= 16 f
LIN
) 1 Tbit (= 16 f
LIN
)
Start bit
Start bit
Start bit
Byte field
Data (8 bits) Stop bit
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