Renesas RL78 Series User Manual

RL78/F13, F14 CHAPTER 17 LIN/UART MODULE (RLIN3)
R01UH0368EJ0210 Rev.2.10 1249
Dec 10, 2015
17.6.5 Reception in LIN Slave Self-Test Mode
To execute a self-test on LIN slave reception, perform the procedure below:
 Set registers related to the baud rate, noise filter, and interrupt output.
LWBRn register = 0000xxx0b
Note 1
LBRPn0 register = xxxxxxxxb
Note 1
LBRPn1 register = xxxxxxxxb
Note 1
LMDn register = 00xx0011b
Note 4
 Set registers related to interrupt enabling and error enabling.
LIEn register = 0000xxxxb
Note 2, 4
LEDEn register = xx0xx00xb
 Set registers related to the break field and spaces.
LBFCn register = 0000000xb
Note 3
LSCn register = 00xx0001b
Note 1
 Cancel the reset.
Write 11b to the OM1 and OM0 bits in the LCUCn register and verify that the OMM1 and OMM0 bits in the LMSTn
register become 11b.
 Set registers related to the reception frame.
LDFCn register = 00x0xxxxb
LIDBn register = xxxxxxxxb
LDBn1 to LDBn8 registers = xxxxxxxxb
LCBRn register = xxxxxxxxb
Since the checksum is not computed automatically, store a computed value. By intentionally setting an incorrect
computation result as the checksum, a test for checksum errors can be performed.
 Start header reception followed with response reception
Set the FTS bit in the LTRCn register to 1 (header reception or wake-up transmission/reception started).
(Without any operation involving the RTS bit in the LTRCn register, the reception of a header and the reception of a
response are executed, in the indicated order.)
The LIN slave self-test mode (reception) is executed. In this mode, interrupts are generated, and status and error status are
also updated appropriately. When the execution of LIN master self-test mode (reception) is aborted, set OM0 bit of LCUCn
register to 0 (LIN reset mode).
 When the reception is completed, the reversed value of the looped-back frame data is stored in the LIDBn, LDBnm
(m = 1 to 8), and LCBRn registers (the data is reversed before being stored because the set value should be
compared with the looped-back and received value). The FTS bit in the LTRCn register is cleared.
 If the reception fails to complete due to an error, the applicable error flag is set and the FTS bit in the LTRCn register
is cleared.
Notes 1. The following register settings do not affect the operations in LIN self-test mode. Therefore, setting them is
not mandatory.
LPRS bits in LWBRn register, LBRPn0 register, LBRPn1 register, and IBS bits in LSCn register
2. As necessary, set the related registers in CHAPTER 21 INTERRUPT FUNCTIONS.
3. A break with a width of 9.5 or 10.5 Tbits is output from the internal LTXDn pin depending on this register
setting.
4. When the successful header reception interrupt and successful response reception interrupt are used in the
same interrupt, the SHIE bit in the LIEn register should not be set to 1 (successful header reception
interrupt enabled) if the software processing of the successful header reception interrupt does not complete
before the successful response reception interrupt is generated.
The period starting from when the successful header reception flag is set until the successful
response/wake-up reception flag is set can be calculated as follows:
10  (number of data bytes + 1) [Tbit]
1 Tbit = LIN communication clock source  16
Remark x: Any desired value
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Renesas RL78 Series Specifications

General

Brand	Renesas
Model	RL78 Series
Category	Computer Hardware
Language	English