Renesas RL78 Series User Manual

RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT
R01UH0368EJ0210 Rev.2.10 542
Dec 10, 2015
6.9 Cautions When Using Timer Array Unit
6.9.1 Cautions When Using Timer output
(1) When the PCLK (not divided) is selected as the operating clock for the timer array unit and TDRnm (n = 0, 1; m = 0
to 7) are set to 0000H, an interrupt signal from the timer array unit is fixed to high, and an interrupt request cannot
be detected.
To use this setting, the interrupt function should be masked.
(2) Do not change the input source for the timer set by the TIS0, TIS1, and TIS2 registers while the timer operates.

Renesas RL78 Series Specifications

General

Core	RL78
CPU Clock Speed	Up to 32 MHz
Flash Memory	Up to 512 KB
RAM	Up to 32 KB
Operating Voltage	1.6 V to 5.5 V
Low Power Modes	HALT, STOP, SNOOZE
CPU Architecture	16-bit
Temperature Range	-40°C to +85°C
Package	LQFP
Timers	16-bit timers
Communication Interfaces	UART, I2C, LIN
A/D Converter	12-bit