Renesas RL78 Series User Manual

RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR
R01UH0368EJ0210 Rev.2.10 423
Dec 10, 2015
5.7 Usage Notes
5.7.1 CPU/Peripheral Hardware Clock
The clock set by the CSS, MCM0, SELPLL, and MDIV2 to MDIV0 bits is supplied to the CPU and peripheral hardware
modules. If the CPU clock is changed, the clock supplied to the peripheral hardware modules is simultaneously changed.
Therefore, when changing the CPU/peripheral hardware clock, operation of the peripheral hardware modules needs to be
stopped before the change.
5.7.2 High-Speed On-Chip Oscillator
When the FRQSEL3 bit is set to 0 (high-speed on-chip oscillator = 48/24/12/6/3 MHz), and moreover the CPU/peripheral
hardware clock is selected as the PLL clock, the CPU/peripheral hardware clock frequency (fCLK) must not be set to 32 MHz.
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Renesas RL78 Series Specifications

General

Brand	Renesas
Model	RL78 Series
Category	Computer Hardware
Language	English