Renesas RL78 Series User Manual

RL78/F13, F14 CHAPTER 36 ELECTRICAL SPECIFICATIONS (GRADE Y)
R01UH0368EJ0210 Rev.2.10 1821
Dec 10, 2015
36.5.2 Serial Interface IICA
(TA = -40 to +150C, 2.7 V  EVDD0 = EVDD1 = VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
Parameter Symbol Conditions Normal Mode Fast Mode Fast Mode Plus Unit
MIN. MAX. MIN. MAX. MIN. MAX.
SCLA0 clock frequency
f
SCL
Fast mode plus:
10 MHz  f
CLK
0 1000 kHz
Fast mode:
3.5 MHz  f
CLK
0 400 kHz
Normal mode:
1 MHz  f
CLK
0 100 kHz
Setup time of restart
condition
Note 1
t
SU:STA 4.7 0.6 0.26 µs
Hold time
t
HD:STA 4.0 0.6 0.26 µs
Hold time when SCLA0 = ”L”
t
LOW 4.7 1.3 0.5 µs
Hold time when SCLA0 = ”H”
t
HIGH 4.0 0.6 0.26 µs
Data setup time (reception)
t
SU:DAT 250 100 50 ns
Data hold time
(transmission)
Note 2
t
HD:DAT 0 3.45 0 0.9 0 µs
Setup time of stop condition
t
SU:STO 4.0 0.6 0.26 µs
Bus-free time
t
BUF 4.7 1.3 0.5 µs
Notes 1. The first clock pulse is generated after this period when the start/restart condition is detected.
2. The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK
(acknowledge) timing.
Remark The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up
resistor) at that time in each mode are as follows.
Standard mode: C
b = 400 pF, Rb = 2.7 kΩ
Fast mode: C
b = 320 pF, Rb = 1.1 kΩ
Fast mode plus: C
b = 120 pF, Rb = 1.1 kΩ
IICA serial transfer timing
t LOW t R
t HIGH t F
t HD:STA
t BUF
Stop
condition
Start
condition
Restart
condition
Stop
condition
t SU:DAT
t SU:STA t SU:STO t HD:STA
t HD:DAT
SCLA0
SDAA0

Renesas RL78 Series Specifications

General

Brand	Renesas
Model	RL78 Series
Category	Computer Hardware
Language	English