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RL78/F13, F14 CHAPTER 19 DTC

R01UH0368EJ0210 Rev.2.10 1460

Dec 10, 2015

19.4 Notes on DTC

19.4.1 Setting DTC Registers and Vector Table

 Do not access the DTC SFRs, the DTC control data area, the DTC vector table area, or the general-register (FFEE0H

to FFEFFH) space using a DTC transfer.

 Modify the DTC base address register (DTCBAR) while all DTC activation sources are set to activation disabled.

 Do not rewrite the DTC base address register (DTCBAR) twice or more.

 Modify the data of the DTCCRj, DTBLSj, DTCCTj, DTRLDj, DTSARj, or DTDARj register when the corresponding bit

among bits DTCENi0 to DTCENi7 in the DTCENi (i = 0 to 5

Note

) register is 0 (DTC activation disabled).

 Modify the start address of the DTC control data area to be set in the vector table when the corresponding bit among

bits DTCENi0 to DTCENi7 in the DTCENi (i = 0 to 5

Note

) register is 0 (DTC activation disabled).

Note Products of groups A, B, C, and D: i = 0 to 4

Products of group E: i = 0 to 5

19.4.2 Allocation of DTC Control Data Area and DTC Vector Table Area

The areas where the DTC control data and vector table can be allocated differ, depending on the usage conditions.

 It is prohibited to use the general-purpose register (FFF00H to FFEE0H) space as the DTC control data area or DTC

vector table area.

 The 18-byte area between the DTC vector table area and the DTC control data area is a reserved area to be used when

the number of DTC activation sources is expanded.

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