Renesas RL78 Series User Manual

RL78/F13, F14 CHAPTER 11 WATCHDOG TIMER
R01UH0368EJ0210 Rev.2.10 697
Dec 10, 2015
4. The operation of the watchdog timer in the HALT, STOP, and SNOOZE modes differs as follows
depending on the set value of bit 0 (WDSTBYON) and bit 4 (WDTON) of the option byte (000C0H).
WDTON = 1 and WDSTBYON = 0 WDTON = 1 and WDSTBYON = 1
In HALT mode Watchdog timer operation stops. Watchdog timer operation continues.
In STOP mode
In SNOOZE mode
If WDSTBYON = 0, the watchdog timer resumes counting after the HALT, STOP, or SNOOZE
modes is released. At this time, the counter is cleared to 0 and counting starts.
When operating with the X1 oscillation clock after releasing the STOP mode, the CPU starts
operating after the oscillation stabilization time has elapsed.
Therefore, if the period between the STOP mode release and the watchdog timer overflow is short,
an overflow occurs during the oscillation stabilization time, causing a reset.
Consequently, set the overflow time in consideration of the oscillation stabilization time when
operating with the X1 oscillation clock and when the watchdog timer counter is to be cleared after
the STOP mode release by an interval interrupt.
11.4.2 Setting overflow time of watchdog timer
Set the overflow time of the watchdog timer by using bits 3 to 1 (WDCS2 to WDCS0) of the option byte (000C0H).
If an overflow occurs, an internal reset signal is generated. The present count is cleared and the watchdog timer starts
counting again by writing “ACH” to the watchdog timer enable register (WDTE) during the window open period before the
overflow time.
The following overflow times can be set.
Table 11-3. Setting of Overflow Time of Watchdog Timer
WDCS2 WDCS1 WDCS0 Overflow Time of Watchdog Timer
(f
WDT = 17.25 kHz (MAX.))
0 0 0 2
6
/fWDT (3.71 ms)
0 0 1 2
7
/fWDT (7.42 ms)
0 1 0 2
8
/fWDT (14.84 ms)
0 1 1 2
9
/fWDT (29.68 ms)
1 0 0 2
11
/fWDT (118.72 ms)
1 0 1 2
13
/fWDT
Note
(474.89 ms)
1 1 0 2
14
/fWDT
Note
(949.79 ms)
1 1 1 2
16
/fWDT
Note
(3799.18 ms)
Note When the interval interrupt of watchdog timer is used, do not set the overflow time to 2
13
/fWDT, 2
14
/fWDT or 2
16
/fWDT.
Remark f
WDT: WDT-dedicated low-speed on-chip oscillator clock frequency
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Renesas RL78 Series Specifications

General

Brand	Renesas
Model	RL78 Series
Category	Computer Hardware
Language	English