RL78/F13, F14 CHAPTER 11 WATCHDOG TIMER
R01UH0368EJ0210 Rev.2.10 698
Dec 10, 2015
11.4.3 Setting window open period of watchdog timer
Set the window open period of the watchdog timer by using bits 6 and 5 (WINDOW1, WINDOW0) of the option byte
(000C0H). The outline of the window is as follows.
If “ACH” is written to the watchdog timer enable register (WDTE) during the window open period, the watchdog timer
counter is cleared and starts counting again.
Even if “ACH” is written to the WDTE register during the window close period, an abnormality is detected and an internal
reset signal is generated.
Example: If the window open period is 50%
Caution When data is written to the WDTE register for the first time after reset release, the watchdog timer
counter is cleared in any timing regardless of the window open time, as long as the register is written
before the overflow time, and the watchdog timer counter starts counting again.
The window open period can be set is as follows.
Table 11-4. Setting Window Open Period of Watchdog Timer
WINDOW1 WINDOW0 Window Open Period of Watchdog Timer
0 0 Setting prohibited
0 1 50%
1 0 75%
1 1 100%
Caution When bit 0 (WDSTBYON) of the option byte (000C0H) = 0, the window open period is 100% regardless
of the values of the WINDOW1 and WINDOW0 bits.
Window close period (50%)
Counting
starts
Overflow
time
Window open period (50%)
Counter value is cleared and
counting starts again when
"ACH" is written to WDTE.
Internal reset signal is generated
if "ACH" is written to WDTE.
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