Renesas RL78 Series User Manual

RL78/F13, F14 CHAPTER 18 CAN INTERFACE (RS-CAN LITE)
R01UH0368EJ0210 Rev.2.10 1387
Dec 10, 2015
18.5 Reception Function
There are two reception types.
• Reception by receive buffers:
Zero to 16 receive buffers can be shared by all channels. Since messages stored in receive buffers are
overwritten at each reception, the latest receive data can always be read.
• Reception by receive FIFO buffers and transmit/receive FIFO buffers (receive mode):
Two receive FIFO buffers can be shared by all channels and one dedicated transmit/receive FIFO buffer is
provided for each channel. The FIFO buffers can hold the number of received messages set by the RFDC[2:0]
bits and CFDC[2:0] bits, and massages can be read sequentially from the oldest.
18.5.1 Data Processing Using the Receive Rule Table
Data processing using the receive rule table allows selected messages to be stored in the specified buffer. Data
processing includes acceptance filter processing, DLC filter processing, routing processing, label addition processing, and
mirror function processing.
Up to 16 receive rules can be registered per channel. If receive rules are not set, no message can be received. Figure
18-4 illustrates how receive rules are registered.
Figure 18-4. Entry of Receive Rules
Each receive rule consists of 12 bytes in the GAFLIDLj, GAFLIDHj, GAFLMLj, GAFLMHj, GAFLPLj, and GAFLPHj
registers (j = 0 to 15). The GAFLIDLj and GAFLIDHj registers (j = 0 to 15) are used to set ID, IDE bit, RTR bit, and the
mirror function, the GAFLMLj and GAFLMHj registers are used to set mask, the GAFLPLj and GAFLPHj registers are used
to set label information to be added, DLC value, and storage receive buffer, and storage FIFO buffer.
(1) Acceptance Filter Processing
In the acceptance filter processing, the ID data, IDE bit, and RTR bit in a received message are compared with the ID
data, IDE bit, and RTR bit set in the receive rule of the corresponding channel. When all these bits match, the message
passes through the acceptance filter processing. The ID data, IDE bit, and RTR bit in a received message which
correspond to bits that are set to 0 (bits are not compared) in the GAFLMLj and GAFLMHj registers are not compared and
are regarded as matched.
Check begins with the receive rule with the smallest rule number of the corresponding channel. When all the bits to be
compared in a received message match the bits set in the receive rule or when all the receive rules are compared without
any match, filter processing stops. If there is no matching receive rule, the received message is not stored in the receive
buffer or FIFO buffer.
Receive rule 0
Receive rule j
Receive rule 1
Receive rule 15
Remark RNC0[4:0]: Bits in the GAFLCFG register
Boundary is determined by
the RNC0[4:0] bits
Channel 0 receive rules 0 to j
j : The value of RNC0[4:0] - 1

Renesas RL78 Series Specifications

General

Brand	Renesas
Model	RL78 Series
Category	Computer Hardware
Language	English