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RL78/F13, F14 CHAPTER 19 DTC

R01UH0368EJ0210 Rev.2.10 1461

Dec 10, 2015

19.4.3 DTC Pending Instruction

If a transfer request is generated from the DTC to the CPU, the DTC is not activated immediately after the following

instructions. Also, the DTC is not activated between PREFIX instruction code and the instruction immediately after that code.

 Call/return instruction

 Unconditional branch instruction

 Conditional branch instruction

 Read access instruction for code flash memory

 Bit manipulation instructions for IFxx, MKxx, PRxx, and PSW, and an 8-bit manipulation instruction that has the ES

 Instruction for accessing the data flash memory

 Multiply, Divide, Multiply & accumulate instruction (exclude MULU instruction)

Cautions 1. On reception of a DTC transfer request, all interrupt requests are held pending until the DTC transfer is

completed.

2. All interrupt requests are also held pending while a DTC transfer is suspended due to a DTC pending

instruction.

19.4.4 Operations when an Instruction which Accesses an SFR Register that Requires a Wait is Executed

DTC transfer is suspended while an instruction which accesses an SFR register

Note

that requires a wait is executed. The

DTC transfer remains suspended as long as polling of the SFR register that requires a wait continues.

Note SFR registers that require a wait are registers of the CAM and LIN modules, and the TRJ0 register of the timer RJ

module.

19.4.5 Operation when Accessing Data Flash Memory Space

Because DTC data transfer is suspended to access the data flash space, be sure to add the DTC pending instruction.

If the data flash space is accessed after an instruction execution from start of DTC data transfer, a 3-clock wait will be

inserted to the next instruction.

Instruction 1

DTC data transfer

Instruction 2 The wait of three clock cycles occurs.

MOV A, ! Data Flash space

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