Renesas RL78 Series User Manual

RL78/F13, F14 CHAPTER 34 ELECTRICAL SPECIFICATIONS (GRADE L)
R01UH0368EJ0210 Rev.2.10 1693
Dec 10, 2015
(T
A = -40 to +105C, 2.7 V  EVDD0 = EVDD1 = VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/3)
Items Symbol Conditions MIN. TYP. MAX. Unit
Supply
current
Notes 1,
3
IDD2
HALT
mode
Note 2
Normal
operation
Note 4
High-speed on-
chip oscillator
clock operation
f
IH = 64 MHz
f
CLK = 32 MHz
Note 6
1.2 10.0 mA
fIH = 32 MHz fCLK = fIH
Note 6
1.0 9.0 mA
fIH = 1 MHz fCLK = fIH
Note 6
0.3 1.5 mA
Resonator
operation
f
MX = 20 MHz fCLK = fMX
Note 7
0.6 6.0 mA
fMX = 1 MHz fCLK = fMX
Note 7
0.2 1.5 mA
Resonator
operation
(PLL
operation)
(PLL input
clock = f
MX)
f
PLL = 64 MHz,
f
MX = 8 MHz
f
CLK = 32 MHz
Note 8
1.1 10.0 mA
fPLL = 32 MHz,
f
MX = 8 MHz
f
CLK = 32 MHz
Note 8
1.0 9.5 mA
fPLL = 32 MHz,
f
MX = 4 MHz
f
CLK = 32 MHz
Note 8
0.8 9.0 mA
Subsystem
clock
operation
f
SUB = 32.768
kHz
f
CLK = fSUB
Note 9
Groups A to D 0.7 45.0 A
Group E 0.7 65.0
Low-speed on-
chip oscillator
clock operation
f
IL = 15 kHz fCLK = fIL
Note 10
Groups A to D 0.7 35.0 A
Group E 0.7 55.0
IDD3
STOP
mode
Note 5
T
A = +25C Groups A to D 0.5 A 
Group E 0.5
TA = +50C Groups A to D 2.5
Group E 4.5
TA = +70C Groups A to D 4.5
Group E 8.0
TA = +105C Groups A to D 30.0
Group E 50.0
Notes 1. Total current flowing into VDD and EVDD0, including the input leakage current flowing when the level of the
input pin is fixed to V
DD, EVDD0, VSS, or EVSS0. However, not including the current flowing into the I/O buffer and
on-chip pull-up/pull-down resistors.
2. When HALT mode is entered during fetch from the flash memory.
3. The values below the MAX. column include the peripheral operation current and STOP leakage current.
However, the watchdog timer, LVD circuit, A/D converter, D/A converter, and comparator are stopped
4. Current flowing when all the instructions are executed by the CPU.
5. When high-speed system clock, subsystem clock, PLL clock, high-speed on-chip oscillator clock, and low-
speed on-chip oscillator clock are stopped.
6. When high-speed system clock, subsystem clock, PLL clock, and low-speed on-chip oscillator clock are
stopped.
7. When subsystem clock, PLL clock, high-speed on-chip oscillator clock, and low-speed on-chip oscillator
clock are stopped.
8. When subsystem clock, high-speed on-chip oscillator clock, and low-speed on-chip oscillator clock are
stopped.

Renesas RL78 Series Specifications

General

Brand	Renesas
Model	RL78 Series
Category	Computer Hardware
Language	English