Renesas RL78 Series User Manual

RL78/F13, F14 CHAPTER 8 TIMER RD
R01UH0368EJ0210 Rev.2.10 655
Dec 10, 2015
When the value in the buffer register is set to 0000H (duty cycle is 100%):
Transfer takes place at compare match between registers TRD0 and TRDGRA0.
After this, when the buffer register is set to 0001H or above and a smaller value than the value of the TRDGRA0
register, and a compare match occurs between registers TRD0 and TRDGRA0 for the first time after setting, the
value is transferred to the general register. After that, the value is transferred with the timing selected by bits CMD0
and CMD1. A direct change of the duty from 100% to 0% is not possible.
Figure 8-66. Operation When Value in Buffer Register is Set to 0000H in Complementary PWM Mode
0000H
TRDGRD0 register
TRDIOB0 output
n1
m+1
n2
n1
0000H n1
0000H
n1 n1n2
TRDGRB0 register
Transfer at compare
match between
registers TRD0 and
TRDGRA0 because
content in TRDGRD0
register is set to 0000H
Transfer at compare
match between
registers TRD0 and
TRDGRA0 because
of first setting to
0001H  n1 < m
Transfer with timing
set by bits CMD1 and
CMD0
TRDIOD0 output
Remark
m: Value set in TRDGRA0 register
The above diagram applies under the following conditions:
• Bits CMD1 and CMD0 in the TRDFCR register are set to 10B (data in the buffer register is transferred at underflow of the
TRD1 register in PWM mode).
• Both the OLS0 and OLS1 bits in the TRDFCR register are set to 1 (active high for normal-phase and counter-phase).
Count value in TRD0
Count value in TRD1
Transfer with timing
set by bits CMD1
and CMD0
Time
Value in
TRDi register
Transfer Transfer Transfer
Transfer

Renesas RL78 Series Specifications

General

Brand	Renesas
Model	RL78 Series
Category	Computer Hardware
Language	English