98
Intel
®
855GME Chipset and Intel
®
6300ESB ICH Embedded Platform Design Guide
compared to the 17.1 pH (600 pH/35) inductance of the thirty-five 0805 decoupling capacitors.
When alternative layout solutions are used, they shall be implemented with a level of robustness
greater than or equal to that in the previous example. In terms of robustness, this refers to creating
a low resistance and inductance connection between the bulk and mid-frequency capacitors and the
processor pins.
For options 1 to 3 in Table 21, the layout concepts described above and depicted in Figure 42
through Figure 47 are also similar in many respects. The main difference between the layout
implementations of option 4 compared to options 1 to 3 is the use of 0612 reverse geometry
capacitors. To be effective, these 0612 capacitors need to occupy the space within the Intel Pentium
M/Celeron M processor socket cavity shadow on the secondary side for both the north and south
sides of the pin-map as well as outside the socket shadow along the ‘north power corridor’ pins.
Intel recommends the adoption of option 4 for the V
CC-CORE
decoupling. When option 1, 2, or 3 is
used, the arrangement of the V
CC-CORE
/GND vias in the Intel Pentium M/Celeron M processor pin
field is recommended to be refined based on recommendations and layout example described
above.
Figure 44. V
CC-CORE
Power Delivery and Decoupling Example –
Option 4 (Primary and Secondary Side Layers)
Primary Side
Secondary Side
VCCP
To
Odem
1.8v
Sense Resistors
VR Feed
V
CC_COR
VCCP
VCCP
To ITP
V
VCCP
Cross
Section
View
9x10uFx0805
CCA
o Odem
.8v
9x10uFx0805
4x220uF SP Cap
2
1
3
3
+
+
-
+
+
-
+
+
-
+
+
-
8x10uFx0805
Primary Side
Secondary Side
VCCP
To Intel®
855GME
Chipset
1.8v
Sense Resistors
VR Feed
V
CC_COR
VCCP
VCCP
To ITP
V
CC_COR
VCCP
Cross
Section
View
CCA
o Intel®
55GME
hipset
2
1
3
3
+
+
-
+
+
-
+
+
-
+
+
-
L1 PS
L2 GND
L3 Sig
L4 GND
L5 PWR
L6 Sig
L7 GND
L8 SS
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