Memory Interface Routing
R
Intel
®
Pentium
®
4 Processor / Intel
®
850 Chipset Family Platform Design Guide 107
6.1.7 Suspend-to-RAM Shunt Transistor
When the system enters or exits Suspend-to-RAM, power will be ramping to the MCH (i.e., it will
be powering-up or powering-down). When power is ramping, the state of the MCH outputs is not
guaranteed. Therefore, the MCH may drive the CMOS signals and issue CMOS commands. The
only command RDRAM device would respond to is the power-down exit command. To avoid the
MCH inadvertently taking the RDRAM devices out of power-down due to the CMOS interface
being driven during power ramp, the SCK (CMOS clock) signal should be shunted to ground when
the MCH is entering and exiting Suspend-to-RAM. This shunting can be accomplished using the
NPN transistor having a sinking capability of 300 mA @ 400 mV. The transistor should also have
a Cobo of 15 pF or less with a signal switching range of 0.1–1.5 V. Lastly, shunting transistors
must not be having their bases tied directly together. See Figure 71. for the SCK/CMD circuitry.
The following table lists sample transistors that can be used.
Single Package (Q) Series Resistor (R)
MMBT2222LT1D 1 kΩ
MMBT100A 300 Ω
Dual Package
MMDT2222A 1 kΩ
NOTE: The use of these transistors alone does not guarantee the above conditions will be met. Each design
must ensure that the transistor can sink the appropriate amount of current by properly driving the
base. Resistances should include source impedance driver.
To match the electrical characteristics on the SCK signal, the CMD signal needs a dummy
transistor. This transistor’s base should be tied to ground (i.e., always turned off). To minimize
impedance discontinuities, the traces for CMD and SCK must have a neck down from 18 mil
traces to 5 mil traces for 175 mils on either side of the SCK/CMD attach point as shown in Figure
71.
To Next Page
Loading...
Need help?
General
