Intel Pentium 4 User Manual

Platform Clock Routing Guidelines
R
54 Intel
®
Pentium
®
4 Processor / Intel
®
850 Chipset Family Platform Design Guide
4.3.4 Rambus DRCG* Impedance Matching Circuit
The external DRCG impedance matching circuit is shown in Figure 25.
Figure 25. Rambus DRCG* Impedance Matching Network
DRCG
C
D
R
S
R
P
R
T
Z
CH
C
F
V
DD
V
DD
O
V
DD
O
C
D
R
S
C
MID
R
P
Z
CH
C
MID
2
R
T
IR
V
DD
P
V
DD
V
DD
C
IPD
C
D
C
D
C
D
C
D
3.3v
FBead
CBulkCD2
CD2
To 3.3V DRCG
Supply
Connection
DRCG_Imp_Match
Table 7. Rambus DRCG* Impedance Matching Network Values
Component Nominal Value Notes
C
D
0.1 µF Decoupling capacitors to GND
R
S
39 Ω Series termination resistor
R
P
51 Ω Parallel termination resistor
C
MID1
, C
MID2
0.1 µF Virtual GND caps
R
T
27 Ω End of channel termination
C
F
4–15 pF Do Not Stuff, leave pads for future use
FBead 50 Ω @ 100 MHz Ferrite bead
CD2 0.1 µF Additional 3.3 V decoupling caps
CBulk 10 µF Bulk capacitor on device side of ferrite bead
NOTES:
1. Note the removal of the original EMI capacitors between the junctions of RS, RP and ground. These
capacitors had minimal impact on EMI and increased DRCG output jitter by approximately 2X.
2. The intent of component CF is to decouple CLK and CLKB outputs to each other, but data shows this
actually increases device jitter. CF should not be stuffed at this time.
3. The ferrite bead and 10 µF bulk capacitor combination improves jitter and helps to keep the clock noise
away from the rest of the system.
4. 0.1 µF capacitors are better than 0.01 µF or 0.001 µF capacitors for DRCG decoupling.
5. Cmid at 0.1 µF has improved jitter versus Cmid at 100 pF. However, this will increase the latency
coming out of a stop clock or tri-state mode.
6. RS, RP, RT were modified to improve channel signal integrity through increasing CTM/CTMN swing.

Intel Pentium 4 Specifications

General

Brand	Intel
Model	Pentium 4
Category	Computer Hardware
Language	English