Intel Pentium 4 User Manual

Platform Clock Routing Guidelines
R
50 Intel
®
Pentium
®
4 Processor / Intel
®
850 Chipset Family Platform Design Guide
4.3.3.1 Trace Lengths
Figure 20 shows the critical RDRAM device clock routing sections, with the routing lengths for
each section defined in Table 6.
Figure 20. Rambus RDRAM* Device Clock Routing Dimension
RDRAM_Clk_Routing
MCH
DRCG
ABC
TERM
D
Table 6. Rambus RDRAM* Device Clock Routing Guidelines
Clock From
To Length
(inches)
300/400 MHz
RDRAM
Technology
Length
(inches)
533 MHz
RDRAM
Technology
Figure
20
Trace
Rambus DRCG*
Second RIMM*
connector
0.0 – 6.0 0.0 – 6.0 D
RIMM connector RIMM connector 0.4 – 1.0 0.4 – 1.0 B
CTM/CTM#
1
First RIMM
connector
Chipset 1.0 – 6.0 1.0 – 4.0 A
Chipset First RIMM connector 1.0 – 6.0 1.0 – 4.0 A
RIMM connector RIMM connector 0.4 – 1.0 0.4 – 1.0 B
CFM/CFM#
2
Second RIMM
connector
Termination 0.0 – 2.0 0.0 – 2.0 C
NOTES:
1. First RIMM connector to chipset:
Trace length needs to be compensated to match the RSL signals from chipset to first RIMM connector.
2. Chipset to first RIMM connector:
Trace length needs to be compensated to match the RSL signals from first RIMM connector to chipset.
In clock routing sections ‘A’ and ‘D’, it is recommended that the clock signals (CTM/CTM# and
CFM/CFM#) be routed differentially. An example recommended topology for microstrip
differential clock routing is shown in Figure 21.
Note: Clock trace widths and spacing may change with different prepreg thicknesses.

Intel Pentium 4 Specifications

General

Brand	Intel
Model	Pentium 4
Category	Computer Hardware
Language	English