I/O Controller Hub 2
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172 Intel
®
Pentium
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4 Processor / Intel
®
850 Chipset Family Platform Design Guide
9.9.3 Intel
®
82562EH Home/PNA* Guidelines
For correct LAN performance, designers must follow the general guidelines outlined in
Section 9.9.2. Additional guidelines for implementing an 82562EH Home/PNA* LAN connect
component are provided below.
9.9.3.1 Power and Ground Connections
Some rules to follow for power and ground connections:
• For best performance place decoupling capacitors on the backside of the PCB directly under
the 82562EH with equal distance from both pins of the capacitor to power/ground.
The analog power supply pins for 82562EH (VCCA, VSSA) should be isolated from the digital
VCC and VSS through the use of ferrite beads. In addition, adequate filtering and decoupling
capacitors should be provided between VCC and VSS, and VCCA and VSSA power supplies.
9.9.3.2 Guidelines for Intel
®
82562EH Component Placement
Component placement can affect signal quality, emissions, and temperature of a board design.
This section will provide guidelines for component placement.
Careful component placement can:
• Decrease potential problems directly related to electromagnetic interference (EMI), which
could cause failure to meet FCC specifications.
• Simplify the task of routing traces. To some extent, component orientation will affect the
complexity of trace routing. The overall objective is to minimize turns and crossovers
between traces.
Minimizing the amount of space needed for the HomePNA* LAN interface is important because
all other interface will compete for physical space on a motherboard near the connector edge. As
with most subsystems, the HomePNA* LAN circuits need to be as close as possible to the
connector. Thus, it is imperative that all designs be optimized to fit in a very small space.
9.9.3.3 Crystals and Oscillators
To minimize the effects of EMI, clock sources should not be placed near I/O ports or board edges.
Radiation from these devices may be coupled onto the I/O ports or out of the system chassis.
Crystals should also be kept away from the HomePNA magnetics module to prevent interference of
communication. The retaining straps of the crystal (if they should exist) should be grounded to
prevent possibility radiation from the crystal case and the crystal should lay flat against the PC
board to provide better coupling of the electromagnetic fields to the board.
For a noise free and stable operation, place the crystal and associated discretes as close as possible
to 82562EH, keeping the length as short as possible and do not route any noisy signals in this area.