Intel Pentium 4 User Manual

AGP Interface Routing
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114 Intel
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Pentium
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4 Processor / Intel
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850 Chipset Family Platform Design Guide
Strobe signals are not used in the 1x AGP mode. In 2x AGP mode, AD[15:0] and C/BE[1:0]# are
associated with AD_STB0, AD[31:16] and C/BE[3:2]# are associated with AD_STB1, and
SBA[7:0] is associated with SB_STB. In 4X AGP mode, AD[15:0] and C/BE[1:0]# are associated
with AD_STB0 and AD_STB0#, AD[31:16] and C/BE[3:2]# are associated with AD_STB1 and
AD_STB1#, and SBA[7:0] is associated with SB_STB and SB_STB#.
7.1 AGP Routing Guidelines
The following section documents the recommended routing guidelines for Intel 850 chipset-based
designs. All aspects of the interface will be covered from signal trace length to decoupling. These
trace length guidelines apply to ALL of the signals listed as 2X/4X timing domain signals. These
signals should be routed using 5 mil (60 Ω) traces.
These guidelines are not intended to replace thorough system simulations and validation.
7.1.1 1X Timing Domain Signal Routing Guidelines
1x signals should adhere to the follow routing guidelines:
• All 1X timing domain signals maximum trace length is 7.5 inches
• 1X timing domain signals can be routed with 5 mil minimum trace separation
• No trace length matching requirements for 1X timing domain signals
7.1.2 2X/4X Timing Domain Signal Routing Guidelines
The maximum line length and mismatch requirements are dependent on the routing rules used on
the motherboard. These routing rules were created to give design freedom by making tradeoffs
between signal coupling (trace spacing) and line lengths. The maximum length of the AGP
interface defines which set of routing guidelines must be used. Guidelines for short AGP interfaces
(e.g., < 6”) and long AGP interfaces (e.g., > 6” and < 7.25”) are documented separately. The
maximum length that is allowed for the AGP interface is 7.25 inches.
7.1.2.1 Trace Lengths Less Than 6 Inches
If the AGP interface is less than 6 inches with 60 Ω ±10% board impedance, at least 5 mil traces
with at least 15 mils of space (1:3) between signals is required for 2X/4X lines (data and strobes).
These 2X/4X signals must be matched to their associated strobe within ±0.25 inches. For example,
if a set of strobe signals (e.g., AD_STB0 and AD_STB0#) are 5.3 inches long, the data signals
associated to those strobe signals (e.g., AD[15:0] and C/BE[2:0]#), can be 5.05 to 5.55 inches
long. While another strobe set (e.g., SB_STB and SB_STB#) could be 4.2 inches long and the
data signals associated to those strobe signals (e.g., SBA[7:0]) can be 3.95 to 4.45 inches long.
The strobe signals (AD_STB0, AD_STB0#, AD_STB1, AD_STB1#, SB_STB, and SB_STB#)
act as clocks on the source synchronous AGP interface; therefore special care must be taken when
routing these signals. Because each strobe pair is truly a differential pair, the pair should be routed
together (e.g., AD_STB0 and AD_STB0# should be routed next to each other). The two strobes in
a strobe pair should be routed on 5 mil traces with at least 15 mils of space (1:3) between them.
This pair should be separated from the rest of the AGP signals (and all other signals) by at least

Intel Pentium 4 Specifications

General

Brand	Intel
Model	Pentium 4
Category	Computer Hardware
Language	English