Intel Pentium 4 User Manual

Power Distribution Guidelines
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236 Intel
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Pentium
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4 Processor / Intel
®
850 Chipset Family Platform Design Guide
12.6 Intel
®
ICH2 V5REF and Vcc3.3 Sequencing
Requirement
V5REF is the reference voltage for 5 V tolerance on inputs to the ICH2. V5REF must be powered
up before Vcc3_3, or after Vcc3_3 within .7 V. Also, V5REF must power down after Vcc3_3, or
before Vcc3_3 within 0.7 V. The rule must be followed in order to ensure the safety of the ICH2.
If the rule is violated, internal diodes will attempt to draw power sufficient to damage the diodes
from the Vcc3_3 rail. Figure 180 shows a sample implementation of how to satisfy the
V5REF/3.3 V sequencing rule.
This rule also applies to the stand-by rails, but in most platforms, the VccSus3_3 rail is derived
from the VccSus5 and therefore, the VccSus3_3 rail will always come up after the VccSus5 rail.
As a result, V5REF_Sus will always be powered up before VccSus3_3. In platforms that do not
derive the VccSus3_3 rail from the VccSus5 rail, this rule must be comprehended in the platform
design.
As an additional consideration, during suspend, the only signals that are 5 V tolerant capable are
USB OC[3:0]#. If these signals are not needed during suspend, V5REF_SUS can be connected to
either VccSus3_3 or 5V_Always/5V_AUX. If OC[3:0]# is needed during suspend and 5 V
tolerance is required then V5REF_SUS should be connected to 5V_Always/5V_AUX, but if 5 V
tolerance is not needed in suspend, then V5REF_SUS can be connected to either VccSus3_3 or
5 V_Always/5V_AUX rails.
Figure 180. V5REF Sequencing Circuit
Vcc3.3 VCC5
To system To system
VREF
5Vref_circ

Intel Pentium 4 Specifications

General

Architecture	x86
Core Count	1
Microarchitecture	NetBurst
Manufacturer	Intel
Core Names	Willamette, Northwood, Prescott, Cedar Mill
Virtualization Technology	No
Release Date	November 20, 2000
Clock Speed	1.3 GHz to 3.8 GHz
FSB Speed	400 MHz to 1066 MHz
Socket	Socket 423, Socket 478, LGA 775
Introduced	2000
Product Line	Pentium
Front Side Bus	400 MHz to 1066 MHz
Hyper-Threading	Yes (Prescott and later)
64-bit Support	Yes (Prescott and later)
Instruction Set	MMX, SSE, SSE2, SSE3
Discontinued	2008
Process Technology	180 nm, 130 nm, 90 nm, 65 nm
L2 Cache	256 KB, 512 KB, 1 MB, 2 MB
Lithography	180 nm, 130 nm, 90 nm, 65 nm
L1 Cache	8 KB