Intel Pentium 4 User Manual

Platform Clock Routing Guidelines
R
42 Intel
®
Pentium
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4 Processor / Intel
®
850 Chipset Family Platform Design Guide
clock driver’s output parasitics, which would otherwise appear in parallel with the termination
resistor Rt.
The value of Rt should be selected to match the characteristic impedance of the system board and
Rs should be 33 Ω.
Figure 13. Source Shunt Termination
L3
L3
L4
L4'
R T
Processor or
MCH
CLOCK
DRIVER
L1
L1'
RS
LT =
L1+L2+L4
Receiver
pin
CK408
pin
L2'
L2
The goal of constraining all bus clocks to one physical routing layer is to minimize the impact on
skew. Skew results from variations in dielectric constant and impedance due to physical tolerances
of the circuit board material. Routing on internal layers provides the least amount of this variation.
• Requirement: Do not split up the two halves of a differential clock pair between layers
• Goal: Route clocks to all agents on same physical routing layer
General Routing Guidelines
• If a layer transition is required, make sure that skew induced by the vias used to transition
between routing layers is compensated in the traces to other agents
• Layer transitions should only be made between routing layers of the same configuration (i.e.,
stripline layer to stripline layer)
• Keep routes to all agents as short as possible to minimize the cumulative effects of dielectric
constant variations on clock skew
• Do not place vias between adjacent complementary clock traces.
• Vias placed in one half of a differential pair must be matched by a via in the other half.
Differential vias can be placed within length L1, between clock driver and RS, if needed to
shorten length L1.

Intel Pentium 4 Specifications

General

Brand	Intel
Model	Pentium 4
Category	Computer Hardware
Language	English