System Bus Routing
R
Intel
®
Pentium
®
4 Processor / Intel
®
850 Chipset Family Platform Design Guide 83
Figure 50. Pull-Down Circuit
R
1
V
SS
Table 20. Reference Voltage Network Values
Signal R1 R2 Tolerance Figure Notes
HDVREF[3:0] 100 Ω 50 Ω ±1% Figure 49 1,2
HAVREF[1:0] 100 Ω 50 Ω ±1% Figure 49 1,2
CCVREF 100 Ω 50 Ω ±1% Figure 49 1,2
HRCOMP[1:0] 25 Ω — ±1% Figure 50 3
HSWNG[1:0] 50 Ω 100 Ω ±1% Figure 49 4
NOTES:
1. 2/3 VTT Resistor Network
2. Single voltage divider for these signals.
3. Independent of board impedance.
4. 1/3 VTT Resistor Network
5.5.1 Intel
®
MCH System Bus I/O Decoupling Requirements
The primary objective of the decoupling requirements for the chipset is to provide clean power
delivery to the System Bus I/O ring. The split plane nature of chipsets creates this power delivery
concern.
The secondary objective of decoupling at the chipset is to minimize the impact of return path
discontinuities that may occur between the chipset package and the system board. A return path
discontinuity occurs in systems whose signals reference either power or ground, but not both.
While the chipset uses symmetric stripline interconnects that reference the signal to both
VCC_CPU and VSS. Systems that have this type of referencing should use the larger number of
decoupling capacitors listed in the below guidelines for the chipset.
The requirements for the chipset are:
• 4 minimum, 5 preferred 0.1 µF capacitors with 603 packages distributed evenly over the
System Bus data lines
• 2 minimum, 3 preferred 0.1 µF capacitors with 603 packages distributed evenly over the
System Bus address and control lines
• All capacitors placed as close as possible to the MCH package (within 150 mils)
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