Intel Pentium 4 User Manual

I/O Controller Hub 2
R
Intel
®
Pentium
®
4 Processor / Intel
®
850 Chipset Family Platform Design Guide 171
5. Routing the transmit differential traces next to the receive differential traces. The transmit
trace that is closest to one of the receive traces will put more crosstalk onto the closest receive
trace and can greatly degrade the receiver's BER over long cables. After exiting the PLC, the
transmit traces should be kept 0.3 inches or more away from the nearest receive trace. The
only possible exceptions are in the vicinities where the traces enter or exit the magnetics, the
RJ-45/11, and the PLC.
6. Use of an inferior magnetics module. The magnetics modules that we use have been fully
tested for IEEE PLC conformance, long cable BER, and for emissions and immunity. (Inferior
magnetics modules often have less common-mode rejection and/or no auto transformer in the
transmit channel.)
7. Use of an 82555 or 82558 physical layer schematic in a PLC design. The transmit
terminations and decoupling are different. There are also differences in the receive circuit.
Follow the appropriate reference schematic or Application Note.
8. Not using (or incorrectly using) the termination circuits for the unused pins at the RJ-45/11
and for the wire-side center-taps of the magnetics modules. These unused RJ pins and wire-
side center-taps must be correctly referenced to chassis ground via the proper value resistor
and a capacitance or termplane. If these are not terminated properly, there can be emissions
(FCC) problems, IEEE conformance issues, and long cable noise (BER) problems. The
Application Notes have schematics that illustrate the proper termination for these unused RJ
pins and the magnetics center-taps.
9. Incorrect differential trace impedances. It is important to have ~100 Ω impedance between the
two traces within a differential pair. This becomes even more important as the differential
traces become longer. It is very common to see customer designs that have differential trace
impedances between 75 Ω and 85 Ω, even when the designers think they've designed for
100 Ω. [To calculate differential impedance, many impedance calculators only multiply the
single-ended impedance by two. This does not take into account edge-to-edge capacitive
coupling between the two traces. When the two traces within a differential pair are kept close
†
to each other the edge coupling can lower the effective differential impedance by
5 to 20 Ω. A 10 to 15 Ω drop in impedance is common.] Short traces will have fewer
problems if the differential impedance is a little off.
10. Use of capacitor that is too large between the transmit traces and/or too much capacitance
from the magnetic's transmit center-tap (on the 82562ET side of the magnetics) to ground.
Using capacitors more than a few pF in either of these locations can slow the 100 Mbps rise
and fall time so much that they fail the IEEE rise time and fall time specs. This will also cause
return loss to fail at higher frequencies and will degrade the transmit BER performance.
Caution should be exercised if a capacitor is put in either of these locations. If a capacitor is
used, it should almost certainly be less than 22 pF. [6 pF to 12 pF values have been used on
past designs with reasonably good success.] These capacitors are not necessary, unless there is
some overshoot in 100 Mbps mode.
Note: It is important to keep the two traces within a differential pair close
†
to each other. Keeping them
close
†
helps to make them more immune to crosstalk and other sources of common-mode noise.
This also means lower emissions (i.e., FCC compliance) from the transmit traces, and better
receive BER for the receive traces.
†
Close should be considered to be less than 0.030 inches
between the two traces within a differential pair. 0.008 inch to 0.012 inch trace-to-trace spacing is
recommended.

Intel Pentium 4 Specifications

General

Brand	Intel
Model	Pentium 4
Category	Computer Hardware
Language	English