R8C/20 Group, R8C/21 Group 12. Interrupts
Rev.2.00 Aug 27, 2008 Page 110 of 458
REJ09B0250-0200
12.6 Notes on Interrupts
12.6.1 Reading Address 00000h
Do not read the address 00000h by a program. When a maskable interrupt request is acknowledged, the CPU
reads interrupt information (interrupt number and interrupt request level) from 00000h in the interrupt
sequence. At this time, the acknowledged interrupt IR bit is set to 0.
If the address 00000h is read in a program, the IR bit for the interrupt which has the highest priority among the
enabled interrupts is set to 0. This may cause a problem that the interrupt is canceled, or an unexpected interrupt
is generated.
12.6.2 SP Setting
Set any value in the SP before an interrupt is acknowledged. The SP is set to 0000h after reset. Therefore, if an
interrupt is acknowledged before setting any value in the SP, the program may run out of control.
12.6.3 External Interrupt and Key Input Interrupt
Either an “L” level or an “H” level of width shown in the Electrical Characteristics is necessary for the signal
input to the INT0
to INT3 pins and KI0 to KI3 pins regardless of the CPU clocks. For details, refer to Table
20.19 External Interrupt INTi
(i = 0 to 3) Input, Table 20.25 External Interrupt INTi (i = 0 to 3) Input.
To Next Page
Loading...
Need help?
General
