R8C/20 Group, R8C/21 Group 5. Resets
Rev.2.00 Aug 27, 2008 Page 27 of 458
REJ09B0250-0200
5.3 Voltage Monitor 1 Reset
A reset is applied using the on-chip voltage detection 1 circuit. The voltage detection 1 circuit monitors the input
voltage to the VCC pin. The voltage to monitor is Vdet1.
When the input voltage to the VCC pin reaches to the Vdet1 level or below, the pins, CPU, and SFR are reset.
And when the input voltage to the VCC pin reaches to the Vdet1 level or above, count operation of the low-speed
on-chip oscillator clock starts. When the operation counts the low-speed on-chip oscillator clock for 32 times, the
internal reset signal is held “H” and the MCU enters the reset sequence (refer to Figure 5.3). The low-speed on-
chip oscillator clock divide-by-8 is automatically selected for the CPU after reset.
The LVD1ON bit in the OFS register can select to enable or disable voltage monitor 1 reset after a reset.
To use the power-on reset function, enable voltage monitor 1 reset by setting the LVD1ON bit in the OFS register
to 0, bits VW1C0 and VW1C6 in the VW1C register to 1, the VCA bit in the VCA2 register to 1.
The LVD1ON bit cannot be changed by a program. When setting the LVD1ON bit, write 0 (voltage monitor 1
reset enabled after reset) or 1 (voltage monitor 1 reset disabled after reset) to the bit 6 of address 0FFFFh using a
flash programmer. Refer to Figure 5.4 OFS Register for details of the OFS register.
Refer to 4. Special Function Registers (SFRs) for the status of the SFR after voltage monitor 1 reset.
The internal RAM is not reset. When the input voltage to the VCC pin reaches to the Vdet1 level or below during
writing to the internal RAM, the internal RAM is in indeterminate state.
Refer to 6. Voltage Detection Circuit for details of voltage monitor 1 reset.
5.4 Voltage Monitor 2 Reset
A reset is applied using the on-chip voltage detection 2 circuit. The voltage detection 2 circuit monitors the input
voltage to the VCC pin. The voltage to monitor is Vdet2.
When the input voltage to the VCC pin drops to the Vdet2 level or below, the pins, CPU, and SFR are reset and the
program is executed beginning with the address indicated by the reset vector. After reset, the low-speed on-chip
oscillator clock divide-by-8 is automatically selected for the CPU clock.
The voltage monitor 2 does not reset some SFRs. Refer to 4. Special Function Registers (SFRs) for details.
The internal RAM is not reset. When the input voltage to the VCC pin reaches to the Vdet2 level or below during
writing to the internal RAM, the internal RAM is in indeterminate state.
Refer to 6. Voltage Detection Circuit for details of voltage monitor 2 reset.
5.5 Watchdog Timer Reset
When the PM12 bit in the PM1 register is set to 1 (reset when watchdog timer underflows), the MCU resets its
pins, CPU, and SFR if the watchdog timer underflows. Then the program is executed beginning with the address
indicated by the reset vector. After reset, the low-speed on-chip oscillator clock divide-by-8 is automatically
selected for the CPU clock.
The watchdog timer reset does not reset some SFRs. Refer to 4. Special Function Registers (SFRs) for details.
The internal RAM is not reset. When the watchdog timer underflows, the internal RAM is in indeterminate state.
Refer to 13. Watchdog Timer for watchdog timer.
5.6 Software Reset
When the PM03 bit in the PM0 register is set to 1 (MCU reset), the MCU resets its pins, CPU, and SFR. The
program is executed beginning with the address indicated by the reset vector. After reset, the low-speed on-chip
oscillator clock divide-by-8 is automatically selected for the CPU clock.
The software reset does not reset some SFRs. Refer to 4. Special Function Registers (SFRs) for details.
The internal RAM is not reset.
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